0001
0002
0003
0004
0005
0006
0007
0008 @@ debug using ARM EmbeddedICE DCC channel
0009
0010 .macro addruart, rp, rv, tmp
0011 .endm
0012
0013 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
0014
0015 .macro senduart, rd, rx
0016 mcr p14, 0, \rd, c0, c5, 0
0017 .endm
0018
0019 .macro busyuart, rd, rx
0020 1001:
0021 mrc p14, 0, \rx, c0, c1, 0
0022 tst \rx, #0x20000000
0023 beq 1001b
0024 .endm
0025
0026 .macro waituartcts, rd, rx
0027 .endm
0028
0029 .macro waituarttxrdy, rd, rx
0030 mov \rd, #0x2000000
0031 1001:
0032 subs \rd, \rd, #1
0033 bmi 1002f
0034 mrc p14, 0, \rx, c0, c1, 0
0035 tst \rx, #0x20000000
0036 bne 1001b
0037 1002:
0038 .endm
0039
0040 #elif defined(CONFIG_CPU_XSCALE)
0041
0042 .macro senduart, rd, rx
0043 mcr p14, 0, \rd, c8, c0, 0
0044 .endm
0045
0046 .macro busyuart, rd, rx
0047 1001:
0048 mrc p14, 0, \rx, c14, c0, 0
0049 tst \rx, #0x10000000
0050 beq 1001b
0051 .endm
0052
0053 .macro waituartcts, rd, rx
0054 .endm
0055
0056 .macro waituarttxrdy, rd, rx
0057 mov \rd, #0x10000000
0058 1001:
0059 subs \rd, \rd, #1
0060 bmi 1002f
0061 mrc p14, 0, \rx, c14, c0, 0
0062 tst \rx, #0x10000000
0063 bne 1001b
0064 1002:
0065 .endm
0066
0067 #else
0068
0069 .macro senduart, rd, rx
0070 mcr p14, 0, \rd, c1, c0, 0
0071 .endm
0072
0073 .macro busyuart, rd, rx
0074 1001:
0075 mrc p14, 0, \rx, c0, c0, 0
0076 tst \rx, #2
0077 beq 1001b
0078
0079 .endm
0080
0081 .macro waituartcts, rd, rx
0082 .endm
0083
0084 .macro waituarttxrdy, rd, rx
0085 mov \rd, #0x2000000
0086 1001:
0087 subs \rd, \rd, #1
0088 bmi 1002f
0089 mrc p14, 0, \rx, c0, c0, 0
0090 tst \rx, #2
0091 bne 1001b
0092 1002:
0093 .endm
0094
0095 #endif