include/debug/exynos.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
0004  *      http://www.samsung.com
0005  */
0006
0007 /* pull in the relevant register and map files. */
0008
0009 #define S3C_ADDR_BASE   0xF6000000
0010 #define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
0011 #define EXYNOS4_PA_UART 0x13800000
0012 #define EXYNOS5_PA_UART 0x12C00000
0013
0014     /* note, for the boot process to work we have to keep the UART
0015      * virtual address aligned to an 1MiB boundary for the L1
0016      * mapping the head code makes. We keep the UART virtual address
0017      * aligned and add in the offset when we load the value here.
0018      */
0019
0020     .macro addruart, rp, rv, tmp
0021         mrc p15, 0, \tmp, c0, c0, 0
0022         and \tmp, \tmp, #0xf0
0023         teq \tmp, #0xf0     @@ A15
0024         beq 100f
0025         mrc p15, 0, \tmp, c0, c0, 5
0026         and \tmp, \tmp, #0xf00
0027         teq \tmp, #0x100        @@ A15 + A7 but boot to A7
0028 100:        ldreq   \rp, =EXYNOS5_PA_UART
0029         movne   \rp, #EXYNOS4_PA_UART   @@ EXYNOS4
0030         ldr \rv, =S3C_VA_UART
0031 #if CONFIG_DEBUG_S3C_UART != 0
0032         add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
0033         add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
0034 #endif
0035     .endm
0036
0037 #define fifo_full fifo_full_s5pv210
0038 #define fifo_level fifo_level_s5pv210
0039
0040 #include <debug/samsung.S>