include/debug/brcmstb.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (C) 2016 Broadcom */
0003 #include <linux/serial_reg.h>
0004 #include <asm/cputype.h>
0005
0006 /* Physical register offset and virtual register offset */
0007 #define REG_PHYS_BASE       0xf0000000
0008 #define REG_PHYS_BASE_V7    0x08000000
0009 #define REG_VIRT_BASE       0xfc000000
0010 #define REG_PHYS_ADDR(x)    ((x) + REG_PHYS_BASE)
0011 #define REG_PHYS_ADDR_V7(x) ((x) + REG_PHYS_BASE_V7)
0012
0013 /* Product id can be read from here */
0014 #define SUN_TOP_CTRL_BASE   REG_PHYS_ADDR(0x404000)
0015 #define SUN_TOP_CTRL_BASE_V7    REG_PHYS_ADDR_V7(0x404000)
0016
0017 #define UARTA_3390      REG_PHYS_ADDR(0x40a900)
0018 #define UARTA_72116     UARTA_7255
0019 #define UARTA_7250      REG_PHYS_ADDR(0x40b400)
0020 #define UARTA_7255      REG_PHYS_ADDR(0x40c000)
0021 #define UARTA_7260      UARTA_7255
0022 #define UARTA_7268      UARTA_7255
0023 #define UARTA_7271      UARTA_7268
0024 #define UARTA_7278      REG_PHYS_ADDR_V7(0x40c000)
0025 #define UARTA_7216      UARTA_7278
0026 #define UARTA_72164     UARTA_7278
0027 #define UARTA_72165     UARTA_7278
0028 #define UARTA_7364      REG_PHYS_ADDR(0x40b000)
0029 #define UARTA_7366      UARTA_7364
0030 #define UARTA_74371     REG_PHYS_ADDR(0x406b00)
0031 #define UARTA_7439      REG_PHYS_ADDR(0x40a900)
0032 #define UARTA_7445      REG_PHYS_ADDR(0x40ab00)
0033
0034 #define UART_SHIFT      2
0035
0036 #define checkuart(rp, rv, family_id, family) \
0037         /* Load family id */ \
0038         ldr rp, =family_id ; \
0039         /* Compare SUN_TOP_CTRL value against it */ \
0040         cmp rp, rv ; \
0041         /* Passed test, load address */ \
0042         ldreq   rp, =UARTA_##family ; \
0043         /* Jump to save UART address */ \
0044         beq 91f
0045
0046         .macro  addruart, rp, rv, tmp
0047         adr \rp, 99f        @ actual addr of 99f
0048         ldr \rv, [\rp]      @ linked addr is stored there
0049         sub \rv, \rv, \rp       @ offset between the two
0050         ldr \rp, [\rp, #4]      @ linked brcmstb_uart_config
0051         sub \tmp, \rp, \rv      @ actual brcmstb_uart_config
0052         ldr \rp, [\tmp]     @ Load brcmstb_uart_config
0053         cmp \rp, #1         @ needs initialization?
0054         bne 100f            @ no; go load the addresses
0055         mov \rv, #0         @ yes; record init is done
0056         str \rv, [\tmp]
0057
0058         /* Check for V7 memory map if B53 */
0059         mrc p15, 0, \rv, c0, c0, 0  @ get Main ID register
0060         ldr \rp, =ARM_CPU_PART_MASK
0061         and \rv, \rv, \rp
0062         ldr \rp, =ARM_CPU_PART_BRAHMA_B53   @ check for B53 CPU
0063         cmp \rv, \rp
0064         bne 10f
0065
0066         /* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */
0067         mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
0068         ands    \rv, \rv, #REG_PHYS_BASE
0069         ldreq   \rp, =SUN_TOP_CTRL_BASE_V7
0070
0071         /* Check SUN_TOP_CTRL base */
0072 10:     ldrne   \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
0073         ldr \rv, [\rp, #0]      @ get register contents
0074 ARM_BE8(    rev \rv, \rv )
0075         and \rv, \rv, #0xffffff00   @ strip revision bits [7:0]
0076
0077         /* Chip specific detection starts here */
0078 20:     checkuart(\rp, \rv, 0x33900000, 3390)
0079 21:     checkuart(\rp, \rv, 0x07211600, 72116)
0080 22:     checkuart(\rp, \rv, 0x72160000, 7216)
0081 23:     checkuart(\rp, \rv, 0x07216400, 72164)
0082 24:     checkuart(\rp, \rv, 0x07216500, 72165)
0083 25:     checkuart(\rp, \rv, 0x72500000, 7250)
0084 26:     checkuart(\rp, \rv, 0x72550000, 7255)
0085 27:     checkuart(\rp, \rv, 0x72600000, 7260)
0086 28:     checkuart(\rp, \rv, 0x72680000, 7268)
0087 29:     checkuart(\rp, \rv, 0x72710000, 7271)
0088 30:     checkuart(\rp, \rv, 0x72780000, 7278)
0089 31:     checkuart(\rp, \rv, 0x73640000, 7364)
0090 32:     checkuart(\rp, \rv, 0x73660000, 7366)
0091 33:     checkuart(\rp, \rv, 0x07437100, 74371)
0092 34:     checkuart(\rp, \rv, 0x74390000, 7439)
0093 35:     checkuart(\rp, \rv, 0x74450000, 7445)
0094
0095         /* No valid UART found */
0096 90:     mov \rp, #0
0097         /* fall through */
0098
0099         /* Record whichever UART we chose */
0100 91:     str \rp, [\tmp, #4]     @ Store in brcmstb_uart_phys
0101         cmp \rp, #0         @ Valid UART address?
0102         bne 92f         @ Yes, go process it
0103         str \rp, [\tmp, #8]     @ Store 0 in brcmstb_uart_virt
0104         b   100f            @ Done
0105 92:     and     \rv, \rp, #0xffffff @ offset within 16MB section
0106         add \rv, \rv, #REG_VIRT_BASE
0107         str \rv, [\tmp, #8]     @ Store in brcmstb_uart_virt
0108         b   100f
0109
0110         .align
0111 99:     .word   .
0112         .word   brcmstb_uart_config
0113         .ltorg
0114
0115         /* Load previously selected UART address */
0116 100:        ldr \rp, [\tmp, #4]     @ Load brcmstb_uart_phys
0117         ldr \rv, [\tmp, #8]     @ Load brcmstb_uart_virt
0118         .endm
0119
0120         .macro  store, rd, rx:vararg
0121 ARM_BE8(    rev \rd, \rd )
0122         str \rd, \rx
0123         .endm
0124
0125         .macro  load, rd, rx:vararg
0126         ldr \rd, \rx
0127 ARM_BE8(    rev \rd, \rd )
0128         .endm
0129
0130         .macro  senduart,rd,rx
0131         store   \rd, [\rx, #UART_TX << UART_SHIFT]
0132         .endm
0133
0134         .macro  busyuart,rd,rx
0135 1002:       load    \rd, [\rx, #UART_LSR << UART_SHIFT]
0136         and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
0137         teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
0138         bne 1002b
0139         .endm
0140
0141         .macro  waituarttxrdy,rd,rx
0142         .endm
0143
0144         .macro  waituartcts,rd,rx
0145         .endm
0146
0147 /*
0148  * Storage for the state maintained by the macros above.
0149  *
0150  * In the kernel proper, this data is located in arch/arm/mach-bcm/brcmstb.c.
0151  * That's because this header is included from multiple files, and we only
0152  * want a single copy of the data. In particular, the UART probing code above
0153  * assumes it's running using physical addresses. This is true when this file
0154  * is included from head.o, but not when included from debug.o. So we need
0155  * to share the probe results between the two copies, rather than having
0156  * to re-run the probing again later.
0157  *
0158  * In the decompressor, we put the symbol/storage right here, since common.c
0159  * isn't included in the decompressor build. This symbol gets put in .text
0160  * even though it's really data, since .data is discarded from the
0161  * decompressor. Luckily, .text is writeable in the decompressor, unless
0162  * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
0163  */
0164 #if defined(ZIMAGE)
0165 brcmstb_uart_config:
0166     /* Debug UART initialization required */
0167     .word 1
0168     /* Debug UART physical address */
0169     .word 0
0170     /* Debug UART virtual address */
0171     .word 0
0172 #endif