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0008 #define AT91_DBGU_SR (0x14)
0009 #define AT91_DBGU_THR (0x1c)
0010 #define AT91_DBGU_TXRDY (1 << 1)
0011 #define AT91_DBGU_TXEMPTY (1 << 9)
0012
0013 .macro addruart, rp, rv, tmp
0014 ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)
0015 ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address)
0016 .endm
0017
0018 .macro senduart,rd,rx
0019 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
0020 .endm
0021
0022 .macro waituarttxrdy,rd,rx
0023 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
0024 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
0025 beq 1001b
0026 .endm
0027
0028 .macro waituartcts,rd,rx
0029 .endm
0030
0031 .macro busyuart,rd,rx
0032 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
0033 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
0034 beq 1001b
0035 .endm
0036