asm/vdso/cp15.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2020 ARM Ltd.
0004  */
0005 #ifndef __ASM_VDSO_CP15_H
0006 #define __ASM_VDSO_CP15_H
0007
0008 #ifndef __ASSEMBLY__
0009
0010 #ifdef CONFIG_CPU_CP15
0011
0012 #include <linux/stringify.h>
0013
0014 #define __ACCESS_CP15(CRn, Op1, CRm, Op2)   \
0015     "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
0016 #define __ACCESS_CP15_64(Op1, CRm)      \
0017     "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
0018
0019 #define __read_sysreg(r, w, c, t) ({                \
0020     t __val;                        \
0021     asm volatile(r " " c : "=r" (__val));           \
0022     __val;                          \
0023 })
0024 #define read_sysreg(...)        __read_sysreg(__VA_ARGS__)
0025
0026 #define __write_sysreg(v, r, w, c, t)   asm volatile(w " " c : : "r" ((t)(v)))
0027 #define write_sysreg(v, ...)        __write_sysreg(v, __VA_ARGS__)
0028
0029 #define BPIALL              __ACCESS_CP15(c7, 0, c5, 6)
0030 #define ICIALLU             __ACCESS_CP15(c7, 0, c5, 0)
0031
0032 #define CNTVCT              __ACCESS_CP15_64(1, c14)
0033
0034 #endif /* CONFIG_CPU_CP15 */
0035
0036 #endif /* __ASSEMBLY__ */
0037
0038 #endif /* __ASM_VDSO_CP15_H */