include/asm/v7m.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Common defines for v7m cpus
0004  */
0005 #define V7M_SCS_ICTR            IOMEM(0xe000e004)
0006 #define V7M_SCS_ICTR_INTLINESNUM_MASK       0x0000000f
0007
0008 #define BASEADDR_V7M_SCB        IOMEM(0xe000ed00)
0009
0010 #define V7M_SCB_CPUID           0x00
0011
0012 #define V7M_SCB_ICSR            0x04
0013 #define V7M_SCB_ICSR_PENDSVSET          (1 << 28)
0014 #define V7M_SCB_ICSR_PENDSVCLR          (1 << 27)
0015 #define V7M_SCB_ICSR_RETTOBASE          (1 << 11)
0016 #define V7M_SCB_ICSR_VECTACTIVE         0x000001ff
0017
0018 #define V7M_SCB_VTOR            0x08
0019
0020 #define V7M_SCB_AIRCR           0x0c
0021 #define V7M_SCB_AIRCR_VECTKEY           (0x05fa << 16)
0022 #define V7M_SCB_AIRCR_SYSRESETREQ       (1 << 2)
0023
0024 #define V7M_SCB_SCR         0x10
0025 #define V7M_SCB_SCR_SLEEPDEEP           (1 << 2)
0026
0027 #define V7M_SCB_CCR         0x14
0028 #define V7M_SCB_CCR_STKALIGN            (1 << 9)
0029 #define V7M_SCB_CCR_DC              (1 << 16)
0030 #define V7M_SCB_CCR_IC              (1 << 17)
0031 #define V7M_SCB_CCR_BP              (1 << 18)
0032
0033 #define V7M_SCB_SHPR2           0x1c
0034 #define V7M_SCB_SHPR3           0x20
0035
0036 #define V7M_SCB_SHCSR           0x24
0037 #define V7M_SCB_SHCSR_USGFAULTENA       (1 << 18)
0038 #define V7M_SCB_SHCSR_BUSFAULTENA       (1 << 17)
0039 #define V7M_SCB_SHCSR_MEMFAULTENA       (1 << 16)
0040
0041 #define V7M_xPSR_FRAMEPTRALIGN          0x00000200
0042 #define V7M_xPSR_EXCEPTIONNO            V7M_SCB_ICSR_VECTACTIVE
0043
0044 /*
0045  * When branching to an address that has bits [31:28] == 0xf an exception return
0046  * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
0047  * extension Bit [4] defines if the exception frame has space allocated for FP
0048  * state information, SBOP otherwise. Bit [3] defines the mode that is returned
0049  * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
0050  * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
0051  */
0052 #define EXC_RET_STACK_MASK          0x00000004
0053 #define EXC_RET_THREADMODE_PROCESSSTACK     (3 << 2)
0054
0055 /* Cache related definitions */
0056
0057 #define V7M_SCB_CLIDR       0x78    /* Cache Level ID register */
0058 #define V7M_SCB_CTR     0x7c    /* Cache Type register */
0059 #define V7M_SCB_CCSIDR      0x80    /* Cache size ID register */
0060 #define V7M_SCB_CSSELR      0x84    /* Cache size selection register */
0061
0062 /* Memory-mapped MPU registers for M-class */
0063 #define MPU_TYPE        0x90
0064 #define MPU_CTRL        0x94
0065 #define MPU_CTRL_ENABLE     1
0066 #define MPU_CTRL_PRIVDEFENA (1 << 2)
0067
0068 #define PMSAv7_RNR      0x98
0069 #define PMSAv7_RBAR     0x9c
0070 #define PMSAv7_RASR     0xa0
0071
0072 #define PMSAv8_RNR      0x98
0073 #define PMSAv8_RBAR     0x9c
0074 #define PMSAv8_RLAR     0xa0
0075 #define PMSAv8_RBAR_A(n)    (PMSAv8_RBAR + 8*(n))
0076 #define PMSAv8_RLAR_A(n)    (PMSAv8_RLAR + 8*(n))
0077 #define PMSAv8_MAIR0        0xc0
0078 #define PMSAv8_MAIR1        0xc4
0079
0080 /* Cache opeartions */
0081 #define V7M_SCB_ICIALLU     0x250   /* I-cache invalidate all to PoU */
0082 #define V7M_SCB_ICIMVAU     0x258   /* I-cache invalidate by MVA to PoU */
0083 #define V7M_SCB_DCIMVAC     0x25c   /* D-cache invalidate by MVA to PoC */
0084 #define V7M_SCB_DCISW       0x260   /* D-cache invalidate by set-way */
0085 #define V7M_SCB_DCCMVAU     0x264   /* D-cache clean by MVA to PoU */
0086 #define V7M_SCB_DCCMVAC     0x268   /* D-cache clean by MVA to PoC */
0087 #define V7M_SCB_DCCSW       0x26c   /* D-cache clean by set-way */
0088 #define V7M_SCB_DCCIMVAC    0x270   /* D-cache clean and invalidate by MVA to PoC */
0089 #define V7M_SCB_DCCISW      0x274   /* D-cache clean and invalidate by set-way */
0090 #define V7M_SCB_BPIALL      0x278   /* D-cache clean and invalidate by set-way */
0091
0092 #ifndef __ASSEMBLY__
0093
0094 enum reboot_mode;
0095
0096 void armv7m_restart(enum reboot_mode mode, const char *cmd);
0097
0098 #endif /* __ASSEMBLY__ */