include/asm/switch_to.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_ARM_SWITCH_TO_H
0003 #define __ASM_ARM_SWITCH_TO_H
0004
0005 #include <linux/thread_info.h>
0006 #include <asm/smp_plat.h>
0007
0008 /*
0009  * For v7 SMP cores running a preemptible kernel we may be pre-empted
0010  * during a TLB maintenance operation, so execute an inner-shareable dsb
0011  * to ensure that the maintenance completes in case we migrate to another
0012  * CPU.
0013  */
0014 #if defined(CONFIG_PREEMPTION) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
0015 #define __complete_pending_tlbi()   dsb(ish)
0016 #else
0017 #define __complete_pending_tlbi()
0018 #endif
0019
0020 /*
0021  * switch_to(prev, next) should switch from task `prev' to `next'
0022  * `prev' will never be the same as `next'.  schedule() itself
0023  * contains the memory barrier to tell GCC not to cache `current'.
0024  */
0025 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
0026
0027 #define switch_to(prev,next,last)                   \
0028 do {                                    \
0029     __complete_pending_tlbi();                  \
0030     if (IS_ENABLED(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || is_smp()) \
0031         __this_cpu_write(__entry_task, next);           \
0032     last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));    \
0033 } while (0)
0034
0035 #endif /* __ASM_ARM_SWITCH_TO_H */