include/asm/pgtable.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/include/asm/pgtable.h
0004  *
0005  *  Copyright (C) 1995-2002 Russell King
0006  */
0007 #ifndef _ASMARM_PGTABLE_H
0008 #define _ASMARM_PGTABLE_H
0009
0010 #include <linux/const.h>
0011 #include <asm/proc-fns.h>
0012
0013 #ifndef CONFIG_MMU
0014
0015 #include <asm-generic/pgtable-nopud.h>
0016 #include <asm/pgtable-nommu.h>
0017
0018 #else
0019
0020 #include <asm-generic/pgtable-nopud.h>
0021 #include <asm/memory.h>
0022 #include <asm/pgtable-hwdef.h>
0023
0024
0025 #include <asm/tlbflush.h>
0026
0027 #ifdef CONFIG_ARM_LPAE
0028 #include <asm/pgtable-3level.h>
0029 #else
0030 #include <asm/pgtable-2level.h>
0031 #endif
0032
0033 /*
0034  * Just any arbitrary offset to the start of the vmalloc VM area: the
0035  * current 8MB value just means that there will be a 8MB "hole" after the
0036  * physical memory until the kernel virtual memory starts.  That means that
0037  * any out-of-bounds memory accesses will hopefully be caught.
0038  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
0039  * area for the same reason. ;)
0040  */
0041 #define VMALLOC_OFFSET      (8*1024*1024)
0042 #define VMALLOC_START       (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
0043 #define VMALLOC_END     0xff800000UL
0044
0045 #define LIBRARY_TEXT_START  0x0c000000
0046
0047 #ifndef __ASSEMBLY__
0048 extern void __pte_error(const char *file, int line, pte_t);
0049 extern void __pmd_error(const char *file, int line, pmd_t);
0050 extern void __pgd_error(const char *file, int line, pgd_t);
0051
0052 #define pte_ERROR(pte)      __pte_error(__FILE__, __LINE__, pte)
0053 #define pmd_ERROR(pmd)      __pmd_error(__FILE__, __LINE__, pmd)
0054 #define pgd_ERROR(pgd)      __pgd_error(__FILE__, __LINE__, pgd)
0055
0056 /*
0057  * This is the lowest virtual address we can permit any user space
0058  * mapping to be mapped at.  This is particularly important for
0059  * non-high vector CPUs.
0060  */
0061 #define FIRST_USER_ADDRESS  (PAGE_SIZE * 2)
0062
0063 /*
0064  * Use TASK_SIZE as the ceiling argument for free_pgtables() and
0065  * free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
0066  * page shared between user and kernel).
0067  */
0068 #ifdef CONFIG_ARM_LPAE
0069 #define USER_PGTABLES_CEILING   TASK_SIZE
0070 #endif
0071
0072 /*
0073  * The pgprot_* and protection_map entries will be fixed up in runtime
0074  * to include the cachable and bufferable bits based on memory policy,
0075  * as well as any architecture dependent bits like global/ASID and SMP
0076  * shared mapping bits.
0077  */
0078 #define _L_PTE_DEFAULT  L_PTE_PRESENT | L_PTE_YOUNG
0079
0080 extern pgprot_t     pgprot_user;
0081 extern pgprot_t     pgprot_kernel;
0082
0083 #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
0084
0085 #define PAGE_NONE       _MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY | L_PTE_NONE)
0086 #define PAGE_SHARED     _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
0087 #define PAGE_SHARED_EXEC    _MOD_PROT(pgprot_user, L_PTE_USER)
0088 #define PAGE_COPY       _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
0089 #define PAGE_COPY_EXEC      _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
0090 #define PAGE_READONLY       _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
0091 #define PAGE_READONLY_EXEC  _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
0092 #define PAGE_KERNEL     _MOD_PROT(pgprot_kernel, L_PTE_XN)
0093 #define PAGE_KERNEL_EXEC    pgprot_kernel
0094
0095 #define __PAGE_NONE     __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
0096 #define __PAGE_SHARED       __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
0097 #define __PAGE_SHARED_EXEC  __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
0098 #define __PAGE_COPY     __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
0099 #define __PAGE_COPY_EXEC    __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
0100 #define __PAGE_READONLY     __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
0101 #define __PAGE_READONLY_EXEC    __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
0102
0103 #define __pgprot_modify(prot,mask,bits)     \
0104     __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
0105
0106 #define pgprot_noncached(prot) \
0107     __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
0108
0109 #define pgprot_writecombine(prot) \
0110     __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
0111
0112 #define pgprot_stronglyordered(prot) \
0113     __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
0114
0115 #define pgprot_device(prot) \
0116     __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)
0117
0118 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
0119 #define pgprot_dmacoherent(prot) \
0120     __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
0121 #define __HAVE_PHYS_MEM_ACCESS_PROT
0122 struct file;
0123 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
0124                      unsigned long size, pgprot_t vma_prot);
0125 #else
0126 #define pgprot_dmacoherent(prot) \
0127     __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
0128 #endif
0129
0130 #endif /* __ASSEMBLY__ */
0131
0132 /*
0133  * The table below defines the page protection levels that we insert into our
0134  * Linux page table version.  These get translated into the best that the
0135  * architecture can perform.  Note that on most ARM hardware:
0136  *  1) We cannot do execute protection
0137  *  2) If we could do execute protection, then read is implied
0138  *  3) write implies read permissions
0139  */
0140
0141 #ifndef __ASSEMBLY__
0142 /*
0143  * ZERO_PAGE is a global shared page that is always zero: used
0144  * for zero-mapped memory areas etc..
0145  */
0146 extern struct page *empty_zero_page;
0147 #define ZERO_PAGE(vaddr)    (empty_zero_page)
0148
0149
0150 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
0151
0152 #define pud_page(pud)       pmd_page(__pmd(pud_val(pud)))
0153 #define pud_write(pud)      pmd_write(__pmd(pud_val(pud)))
0154
0155 #define pmd_none(pmd)       (!pmd_val(pmd))
0156
0157 static inline pte_t *pmd_page_vaddr(pmd_t pmd)
0158 {
0159     return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
0160 }
0161
0162 #define pmd_page(pmd)       pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
0163
0164 #define pte_pfn(pte)        ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
0165 #define pfn_pte(pfn,prot)   __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
0166
0167 #define pte_page(pte)       pfn_to_page(pte_pfn(pte))
0168 #define mk_pte(page,prot)   pfn_pte(page_to_pfn(page), prot)
0169
0170 #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
0171
0172 #define pte_isset(pte, val) ((u32)(val) == (val) ? pte_val(pte) & (val) \
0173                         : !!(pte_val(pte) & (val)))
0174 #define pte_isclear(pte, val)   (!(pte_val(pte) & (val)))
0175
0176 #define pte_none(pte)       (!pte_val(pte))
0177 #define pte_present(pte)    (pte_isset((pte), L_PTE_PRESENT))
0178 #define pte_valid(pte)      (pte_isset((pte), L_PTE_VALID))
0179 #define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
0180 #define pte_write(pte)      (pte_isclear((pte), L_PTE_RDONLY))
0181 #define pte_dirty(pte)      (pte_isset((pte), L_PTE_DIRTY))
0182 #define pte_young(pte)      (pte_isset((pte), L_PTE_YOUNG))
0183 #define pte_exec(pte)       (pte_isclear((pte), L_PTE_XN))
0184
0185 #define pte_valid_user(pte) \
0186     (pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
0187
0188 static inline bool pte_access_permitted(pte_t pte, bool write)
0189 {
0190     pteval_t mask = L_PTE_PRESENT | L_PTE_USER;
0191     pteval_t needed = mask;
0192
0193     if (write)
0194         mask |= L_PTE_RDONLY;
0195
0196     return (pte_val(pte) & mask) == needed;
0197 }
0198 #define pte_access_permitted pte_access_permitted
0199
0200 #if __LINUX_ARM_ARCH__ < 6
0201 static inline void __sync_icache_dcache(pte_t pteval)
0202 {
0203 }
0204 #else
0205 extern void __sync_icache_dcache(pte_t pteval);
0206 #endif
0207
0208 void set_pte_at(struct mm_struct *mm, unsigned long addr,
0209               pte_t *ptep, pte_t pteval);
0210
0211 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
0212 {
0213     pte_val(pte) &= ~pgprot_val(prot);
0214     return pte;
0215 }
0216
0217 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
0218 {
0219     pte_val(pte) |= pgprot_val(prot);
0220     return pte;
0221 }
0222
0223 static inline pte_t pte_wrprotect(pte_t pte)
0224 {
0225     return set_pte_bit(pte, __pgprot(L_PTE_RDONLY));
0226 }
0227
0228 static inline pte_t pte_mkwrite(pte_t pte)
0229 {
0230     return clear_pte_bit(pte, __pgprot(L_PTE_RDONLY));
0231 }
0232
0233 static inline pte_t pte_mkclean(pte_t pte)
0234 {
0235     return clear_pte_bit(pte, __pgprot(L_PTE_DIRTY));
0236 }
0237
0238 static inline pte_t pte_mkdirty(pte_t pte)
0239 {
0240     return set_pte_bit(pte, __pgprot(L_PTE_DIRTY));
0241 }
0242
0243 static inline pte_t pte_mkold(pte_t pte)
0244 {
0245     return clear_pte_bit(pte, __pgprot(L_PTE_YOUNG));
0246 }
0247
0248 static inline pte_t pte_mkyoung(pte_t pte)
0249 {
0250     return set_pte_bit(pte, __pgprot(L_PTE_YOUNG));
0251 }
0252
0253 static inline pte_t pte_mkexec(pte_t pte)
0254 {
0255     return clear_pte_bit(pte, __pgprot(L_PTE_XN));
0256 }
0257
0258 static inline pte_t pte_mknexec(pte_t pte)
0259 {
0260     return set_pte_bit(pte, __pgprot(L_PTE_XN));
0261 }
0262
0263 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
0264 {
0265     const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
0266         L_PTE_NONE | L_PTE_VALID;
0267     pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
0268     return pte;
0269 }
0270
0271 /*
0272  * Encode and decode a swap entry.  Swap entries are stored in the Linux
0273  * page tables as follows:
0274  *
0275  *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
0276  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
0277  *   <--------------- offset ------------------------> < type -> 0 0
0278  *
0279  * This gives us up to 31 swap files and 128GB per swap file.  Note that
0280  * the offset field is always non-zero.
0281  */
0282 #define __SWP_TYPE_SHIFT    2
0283 #define __SWP_TYPE_BITS     5
0284 #define __SWP_TYPE_MASK     ((1 << __SWP_TYPE_BITS) - 1)
0285 #define __SWP_OFFSET_SHIFT  (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
0286
0287 #define __swp_type(x)       (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
0288 #define __swp_offset(x)     ((x).val >> __SWP_OFFSET_SHIFT)
0289 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
0290
0291 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
0292 #define __swp_entry_to_pte(swp) __pte((swp).val | PTE_TYPE_FAULT)
0293
0294 /*
0295  * It is an error for the kernel to have more swap files than we can
0296  * encode in the PTEs.  This ensures that we know when MAX_SWAPFILES
0297  * is increased beyond what we presently support.
0298  */
0299 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
0300
0301 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
0302 /* FIXME: this is not correct */
0303 #define kern_addr_valid(addr)   (1)
0304
0305 /*
0306  * We provide our own arch_get_unmapped_area to cope with VIPT caches.
0307  */
0308 #define HAVE_ARCH_UNMAPPED_AREA
0309 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
0310
0311 #endif /* !__ASSEMBLY__ */
0312
0313 #endif /* CONFIG_MMU */
0314
0315 #endif /* _ASMARM_PGTABLE_H */