include/asm/pgtable-3level.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/include/asm/pgtable-3level.h
0004  *
0005  * Copyright (C) 2011 ARM Ltd.
0006  * Author: Catalin Marinas <catalin.marinas@arm.com>
0007  */
0008 #ifndef _ASM_PGTABLE_3LEVEL_H
0009 #define _ASM_PGTABLE_3LEVEL_H
0010
0011 /*
0012  * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
0013  * 8 bytes each, occupying a 4K page. The first level table covers a range of
0014  * 512GB, each entry representing 1GB. Since we are limited to 4GB input
0015  * address range, only 4 entries in the PGD are used.
0016  *
0017  * There are enough spare bits in a page table entry for the kernel specific
0018  * state.
0019  */
0020 #define PTRS_PER_PTE        512
0021 #define PTRS_PER_PMD        512
0022 #define PTRS_PER_PGD        4
0023
0024 #define PTE_HWTABLE_PTRS    (0)
0025 #define PTE_HWTABLE_OFF     (0)
0026 #define PTE_HWTABLE_SIZE    (PTRS_PER_PTE * sizeof(u64))
0027
0028 #define MAX_POSSIBLE_PHYSMEM_BITS 40
0029
0030 /*
0031  * PGDIR_SHIFT determines the size a top-level page table entry can map.
0032  */
0033 #define PGDIR_SHIFT     30
0034
0035 /*
0036  * PMD_SHIFT determines the size a middle-level page table entry can map.
0037  */
0038 #define PMD_SHIFT       21
0039
0040 #define PMD_SIZE        (1UL << PMD_SHIFT)
0041 #define PMD_MASK        (~((1 << PMD_SHIFT) - 1))
0042 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
0043 #define PGDIR_MASK      (~((1 << PGDIR_SHIFT) - 1))
0044
0045 /*
0046  * section address mask and size definitions.
0047  */
0048 #define SECTION_SHIFT       21
0049 #define SECTION_SIZE        (1UL << SECTION_SHIFT)
0050 #define SECTION_MASK        (~((1 << SECTION_SHIFT) - 1))
0051
0052 #define USER_PTRS_PER_PGD   (PAGE_OFFSET / PGDIR_SIZE)
0053
0054 /*
0055  * Hugetlb definitions.
0056  */
0057 #define HPAGE_SHIFT     PMD_SHIFT
0058 #define HPAGE_SIZE      (_AC(1, UL) << HPAGE_SHIFT)
0059 #define HPAGE_MASK      (~(HPAGE_SIZE - 1))
0060 #define HUGETLB_PAGE_ORDER  (HPAGE_SHIFT - PAGE_SHIFT)
0061
0062 /*
0063  * "Linux" PTE definitions for LPAE.
0064  *
0065  * These bits overlap with the hardware bits but the naming is preserved for
0066  * consistency with the classic page table format.
0067  */
0068 #define L_PTE_VALID     (_AT(pteval_t, 1) << 0)     /* Valid */
0069 #define L_PTE_PRESENT       (_AT(pteval_t, 3) << 0)     /* Present */
0070 #define L_PTE_USER      (_AT(pteval_t, 1) << 6)     /* AP[1] */
0071 #define L_PTE_SHARED        (_AT(pteval_t, 3) << 8)     /* SH[1:0], inner shareable */
0072 #define L_PTE_YOUNG     (_AT(pteval_t, 1) << 10)    /* AF */
0073 #define L_PTE_XN        (_AT(pteval_t, 1) << 54)    /* XN */
0074 #define L_PTE_DIRTY     (_AT(pteval_t, 1) << 55)
0075 #define L_PTE_SPECIAL       (_AT(pteval_t, 1) << 56)
0076 #define L_PTE_NONE      (_AT(pteval_t, 1) << 57)    /* PROT_NONE */
0077 #define L_PTE_RDONLY        (_AT(pteval_t, 1) << 58)    /* READ ONLY */
0078
0079 #define L_PMD_SECT_VALID    (_AT(pmdval_t, 1) << 0)
0080 #define L_PMD_SECT_DIRTY    (_AT(pmdval_t, 1) << 55)
0081 #define L_PMD_SECT_NONE     (_AT(pmdval_t, 1) << 57)
0082 #define L_PMD_SECT_RDONLY   (_AT(pteval_t, 1) << 58)
0083
0084 /*
0085  * To be used in assembly code with the upper page attributes.
0086  */
0087 #define L_PTE_XN_HIGH       (1 << (54 - 32))
0088 #define L_PTE_DIRTY_HIGH    (1 << (55 - 32))
0089
0090 /*
0091  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
0092  */
0093 #define L_PTE_MT_UNCACHED   (_AT(pteval_t, 0) << 2) /* strongly ordered */
0094 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
0095 #define L_PTE_MT_WRITETHROUGH   (_AT(pteval_t, 2) << 2) /* normal inner write-through */
0096 #define L_PTE_MT_WRITEBACK  (_AT(pteval_t, 3) << 2) /* normal inner write-back */
0097 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
0098 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
0099 #define L_PTE_MT_DEV_NONSHARED  (_AT(pteval_t, 4) << 2) /* device */
0100 #define L_PTE_MT_DEV_WC     (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
0101 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
0102 #define L_PTE_MT_MASK       (_AT(pteval_t, 7) << 2)
0103
0104 /*
0105  * Software PGD flags.
0106  */
0107 #define L_PGD_SWAPPER       (_AT(pgdval_t, 1) << 55)    /* swapper_pg_dir entry */
0108
0109 #ifndef __ASSEMBLY__
0110
0111 #define pud_none(pud)       (!pud_val(pud))
0112 #define pud_bad(pud)        (!(pud_val(pud) & 2))
0113 #define pud_present(pud)    (pud_val(pud))
0114 #define pmd_table(pmd)      ((pmd_val(pmd) & PMD_TYPE_MASK) == \
0115                          PMD_TYPE_TABLE)
0116 #define pmd_sect(pmd)       ((pmd_val(pmd) & PMD_TYPE_MASK) == \
0117                          PMD_TYPE_SECT)
0118 #define pmd_large(pmd)      pmd_sect(pmd)
0119 #define pmd_leaf(pmd)       pmd_sect(pmd)
0120
0121 #define pud_clear(pudp)         \
0122     do {                \
0123         *pudp = __pud(0);   \
0124         clean_pmd_entry(pudp);  \
0125     } while (0)
0126
0127 #define set_pud(pudp, pud)      \
0128     do {                \
0129         *pudp = pud;        \
0130         flush_pmd_entry(pudp);  \
0131     } while (0)
0132
0133 static inline pmd_t *pud_pgtable(pud_t pud)
0134 {
0135     return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
0136 }
0137
0138 #define pmd_bad(pmd)        (!(pmd_val(pmd) & 2))
0139
0140 #define copy_pmd(pmdpd,pmdps)       \
0141     do {                \
0142         *pmdpd = *pmdps;    \
0143         flush_pmd_entry(pmdpd); \
0144     } while (0)
0145
0146 #define pmd_clear(pmdp)         \
0147     do {                \
0148         *pmdp = __pmd(0);   \
0149         clean_pmd_entry(pmdp);  \
0150     } while (0)
0151
0152 /*
0153  * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
0154  * that are written to a page table but not for ptes created with mk_pte.
0155  *
0156  * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
0157  * hugetlb_cow, where it is compared with an entry in a page table.
0158  * This comparison test fails erroneously leading ultimately to a memory leak.
0159  *
0160  * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
0161  * present before running the comparison.
0162  */
0163 #define __HAVE_ARCH_PTE_SAME
0164 #define pte_same(pte_a,pte_b)   ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \
0165                     : pte_val(pte_a))               \
0166                 == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG   \
0167                     : pte_val(pte_b)))
0168
0169 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
0170
0171 #define pte_huge(pte)       (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
0172 #define pte_mkhuge(pte)     (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
0173
0174 #define pmd_isset(pmd, val) ((u32)(val) == (val) ? pmd_val(pmd) & (val) \
0175                         : !!(pmd_val(pmd) & (val)))
0176 #define pmd_isclear(pmd, val)   (!(pmd_val(pmd) & (val)))
0177
0178 #define pmd_present(pmd)    (pmd_isset((pmd), L_PMD_SECT_VALID))
0179 #define pmd_young(pmd)      (pmd_isset((pmd), PMD_SECT_AF))
0180 #define pte_special(pte)    (pte_isset((pte), L_PTE_SPECIAL))
0181 static inline pte_t pte_mkspecial(pte_t pte)
0182 {
0183     pte_val(pte) |= L_PTE_SPECIAL;
0184     return pte;
0185 }
0186
0187 #define pmd_write(pmd)      (pmd_isclear((pmd), L_PMD_SECT_RDONLY))
0188 #define pmd_dirty(pmd)      (pmd_isset((pmd), L_PMD_SECT_DIRTY))
0189
0190 #define pmd_hugewillfault(pmd)  (!pmd_young(pmd) || !pmd_write(pmd))
0191 #define pmd_thp_or_huge(pmd)    (pmd_huge(pmd) || pmd_trans_huge(pmd))
0192
0193 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
0194 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !pmd_table(pmd))
0195 #endif
0196
0197 #define PMD_BIT_FUNC(fn,op) \
0198 static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
0199
0200 PMD_BIT_FUNC(wrprotect, |= L_PMD_SECT_RDONLY);
0201 PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
0202 PMD_BIT_FUNC(mkwrite,   &= ~L_PMD_SECT_RDONLY);
0203 PMD_BIT_FUNC(mkdirty,   |= L_PMD_SECT_DIRTY);
0204 PMD_BIT_FUNC(mkclean,   &= ~L_PMD_SECT_DIRTY);
0205 PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
0206
0207 #define pmd_mkhuge(pmd)     (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
0208
0209 #define pmd_pfn(pmd)        (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
0210 #define pfn_pmd(pfn,prot)   (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
0211 #define mk_pmd(page,prot)   pfn_pmd(page_to_pfn(page),prot)
0212
0213 /* No hardware dirty/accessed bits -- generic_pmdp_establish() fits */
0214 #define pmdp_establish generic_pmdp_establish
0215
0216 /* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */
0217 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
0218 {
0219     return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID);
0220 }
0221
0222 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
0223 {
0224     const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | L_PMD_SECT_RDONLY |
0225                 L_PMD_SECT_VALID | L_PMD_SECT_NONE;
0226     pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
0227     return pmd;
0228 }
0229
0230 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
0231                   pmd_t *pmdp, pmd_t pmd)
0232 {
0233     BUG_ON(addr >= TASK_SIZE);
0234
0235     /* create a faulting entry if PROT_NONE protected */
0236     if (pmd_val(pmd) & L_PMD_SECT_NONE)
0237         pmd_val(pmd) &= ~L_PMD_SECT_VALID;
0238
0239     if (pmd_write(pmd) && pmd_dirty(pmd))
0240         pmd_val(pmd) &= ~PMD_SECT_AP2;
0241     else
0242         pmd_val(pmd) |= PMD_SECT_AP2;
0243
0244     *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
0245     flush_pmd_entry(pmdp);
0246 }
0247
0248 #endif /* __ASSEMBLY__ */
0249
0250 #endif /* _ASM_PGTABLE_3LEVEL_H */