include/asm/pgtable-3level-hwdef.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/include/asm/pgtable-3level-hwdef.h
0004  *
0005  * Copyright (C) 2011 ARM Ltd.
0006  * Author: Catalin Marinas <catalin.marinas@arm.com>
0007  */
0008 #ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H
0009 #define _ASM_PGTABLE_3LEVEL_HWDEF_H
0010
0011 /*
0012  * Hardware page table definitions.
0013  *
0014  * + Level 1/2 descriptor
0015  *   - common
0016  */
0017 #define PMD_TYPE_MASK       (_AT(pmdval_t, 3) << 0)
0018 #define PMD_TYPE_FAULT      (_AT(pmdval_t, 0) << 0)
0019 #define PMD_TYPE_TABLE      (_AT(pmdval_t, 3) << 0)
0020 #define PMD_TYPE_SECT       (_AT(pmdval_t, 1) << 0)
0021 #define PMD_TABLE_BIT       (_AT(pmdval_t, 1) << 1)
0022 #define PMD_BIT4        (_AT(pmdval_t, 0))
0023 #define PMD_DOMAIN(x)       (_AT(pmdval_t, 0))
0024 #define PMD_APTABLE_SHIFT   (61)
0025 #define PMD_APTABLE     (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
0026 #define PMD_PXNTABLE        (_AT(pgdval_t, 1) << 59)
0027
0028 /*
0029  *   - section
0030  */
0031 #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2)
0032 #define PMD_SECT_CACHEABLE  (_AT(pmdval_t, 1) << 3)
0033 #define PMD_SECT_USER       (_AT(pmdval_t, 1) << 6)     /* AP[1] */
0034 #define PMD_SECT_AP2        (_AT(pmdval_t, 1) << 7)     /* read only */
0035 #define PMD_SECT_S      (_AT(pmdval_t, 3) << 8)
0036 #define PMD_SECT_AF     (_AT(pmdval_t, 1) << 10)
0037 #define PMD_SECT_nG     (_AT(pmdval_t, 1) << 11)
0038 #define PMD_SECT_PXN        (_AT(pmdval_t, 1) << 53)
0039 #define PMD_SECT_XN     (_AT(pmdval_t, 1) << 54)
0040 #define PMD_SECT_AP_WRITE   (_AT(pmdval_t, 0))
0041 #define PMD_SECT_AP_READ    (_AT(pmdval_t, 0))
0042 #define PMD_SECT_AP1        (_AT(pmdval_t, 1) << 6)
0043 #define PMD_SECT_TEX(x)     (_AT(pmdval_t, 0))
0044
0045 /*
0046  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
0047  */
0048 #define PMD_SECT_UNCACHED   (_AT(pmdval_t, 0) << 2) /* strongly ordered */
0049 #define PMD_SECT_BUFFERED   (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */
0050 #define PMD_SECT_WT     (_AT(pmdval_t, 2) << 2) /* normal inner write-through */
0051 #define PMD_SECT_WB     (_AT(pmdval_t, 3) << 2) /* normal inner write-back */
0052 #define PMD_SECT_WBWA       (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */
0053 #define PMD_SECT_CACHE_MASK (_AT(pmdval_t, 7) << 2)
0054
0055 /*
0056  * + Level 3 descriptor (PTE)
0057  */
0058 #define PTE_TYPE_MASK       (_AT(pteval_t, 3) << 0)
0059 #define PTE_TYPE_FAULT      (_AT(pteval_t, 0) << 0)
0060 #define PTE_TYPE_PAGE       (_AT(pteval_t, 3) << 0)
0061 #define PTE_TABLE_BIT       (_AT(pteval_t, 1) << 1)
0062 #define PTE_BUFFERABLE      (_AT(pteval_t, 1) << 2)     /* AttrIndx[0] */
0063 #define PTE_CACHEABLE       (_AT(pteval_t, 1) << 3)     /* AttrIndx[1] */
0064 #define PTE_AP2         (_AT(pteval_t, 1) << 7)     /* AP[2] */
0065 #define PTE_EXT_SHARED      (_AT(pteval_t, 3) << 8)     /* SH[1:0], inner shareable */
0066 #define PTE_EXT_AF      (_AT(pteval_t, 1) << 10)    /* Access Flag */
0067 #define PTE_EXT_NG      (_AT(pteval_t, 1) << 11)    /* nG */
0068 #define PTE_EXT_PXN     (_AT(pteval_t, 1) << 53)    /* PXN */
0069 #define PTE_EXT_XN      (_AT(pteval_t, 1) << 54)    /* XN */
0070
0071 /*
0072  * 40-bit physical address supported.
0073  */
0074 #define PHYS_MASK_SHIFT     (40)
0075 #define PHYS_MASK       ((1ULL << PHYS_MASK_SHIFT) - 1)
0076
0077 /*
0078  * TTBR0/TTBR1 split (PAGE_OFFSET):
0079  *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
0080  *   0x80000000: T0SZ = 0, T1SZ = 1
0081  *   0xc0000000: T0SZ = 0, T1SZ = 2
0082  *
0083  * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
0084  * booting secondary CPUs would end up using TTBR1 for the identity
0085  * mapping set up in TTBR0.
0086  */
0087 #if defined CONFIG_VMSPLIT_2G
0088 #define TTBR1_OFFSET    16          /* skip two L1 entries */
0089 #elif defined CONFIG_VMSPLIT_3G
0090 #define TTBR1_OFFSET    (4096 * (1 + 3))    /* only L2, skip pgd + 3*pmd */
0091 #else
0092 #define TTBR1_OFFSET    0
0093 #endif
0094
0095 #define TTBR1_SIZE  (((PAGE_OFFSET >> 30) - 1) << 16)
0096
0097 #endif