include/asm/outercache.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/include/asm/outercache.h
0004  *
0005  * Copyright (C) 2010 ARM Ltd.
0006  * Written by Catalin Marinas <catalin.marinas@arm.com>
0007  */
0008
0009 #ifndef __ASM_OUTERCACHE_H
0010 #define __ASM_OUTERCACHE_H
0011
0012 #include <linux/types.h>
0013
0014 struct l2x0_regs;
0015
0016 struct outer_cache_fns {
0017     void (*inv_range)(unsigned long, unsigned long);
0018     void (*clean_range)(unsigned long, unsigned long);
0019     void (*flush_range)(unsigned long, unsigned long);
0020     void (*flush_all)(void);
0021     void (*disable)(void);
0022 #ifdef CONFIG_OUTER_CACHE_SYNC
0023     void (*sync)(void);
0024 #endif
0025     void (*resume)(void);
0026
0027     /* This is an ARM L2C thing */
0028     void (*write_sec)(unsigned long, unsigned);
0029     void (*configure)(const struct l2x0_regs *);
0030 };
0031
0032 extern struct outer_cache_fns outer_cache;
0033
0034 #ifdef CONFIG_OUTER_CACHE
0035 /**
0036  * outer_inv_range - invalidate range of outer cache lines
0037  * @start: starting physical address, inclusive
0038  * @end: end physical address, exclusive
0039  */
0040 static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
0041 {
0042     if (outer_cache.inv_range)
0043         outer_cache.inv_range(start, end);
0044 }
0045
0046 /**
0047  * outer_clean_range - clean dirty outer cache lines
0048  * @start: starting physical address, inclusive
0049  * @end: end physical address, exclusive
0050  */
0051 static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
0052 {
0053     if (outer_cache.clean_range)
0054         outer_cache.clean_range(start, end);
0055 }
0056
0057 /**
0058  * outer_flush_range - clean and invalidate outer cache lines
0059  * @start: starting physical address, inclusive
0060  * @end: end physical address, exclusive
0061  */
0062 static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
0063 {
0064     if (outer_cache.flush_range)
0065         outer_cache.flush_range(start, end);
0066 }
0067
0068 /**
0069  * outer_flush_all - clean and invalidate all cache lines in the outer cache
0070  *
0071  * Note: depending on implementation, this may not be atomic - it must
0072  * only be called with interrupts disabled and no other active outer
0073  * cache masters.
0074  *
0075  * It is intended that this function is only used by implementations
0076  * needing to override the outer_cache.disable() method due to security.
0077  * (Some implementations perform this as a clean followed by an invalidate.)
0078  */
0079 static inline void outer_flush_all(void)
0080 {
0081     if (outer_cache.flush_all)
0082         outer_cache.flush_all();
0083 }
0084
0085 /**
0086  * outer_disable - clean, invalidate and disable the outer cache
0087  *
0088  * Disable the outer cache, ensuring that any data contained in the outer
0089  * cache is pushed out to lower levels of system memory.  The note and
0090  * conditions above concerning outer_flush_all() applies here.
0091  */
0092 extern void outer_disable(void);
0093
0094 /**
0095  * outer_resume - restore the cache configuration and re-enable outer cache
0096  *
0097  * Restore any configuration that the cache had when previously enabled,
0098  * and re-enable the outer cache.
0099  */
0100 static inline void outer_resume(void)
0101 {
0102     if (outer_cache.resume)
0103         outer_cache.resume();
0104 }
0105
0106 #else
0107
0108 static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
0109 { }
0110 static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
0111 { }
0112 static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
0113 { }
0114 static inline void outer_flush_all(void) { }
0115 static inline void outer_disable(void) { }
0116 static inline void outer_resume(void) { }
0117
0118 #endif
0119
0120 #endif  /* __ASM_OUTERCACHE_H */