include/asm/mmu_context.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/include/asm/mmu_context.h
0004  *
0005  *  Copyright (C) 1996 Russell King.
0006  *
0007  *  Changelog:
0008  *   27-06-1996 RMK Created
0009  */
0010 #ifndef __ASM_ARM_MMU_CONTEXT_H
0011 #define __ASM_ARM_MMU_CONTEXT_H
0012
0013 #include <linux/compiler.h>
0014 #include <linux/sched.h>
0015 #include <linux/mm_types.h>
0016 #include <linux/preempt.h>
0017
0018 #include <asm/cacheflush.h>
0019 #include <asm/cachetype.h>
0020 #include <asm/proc-fns.h>
0021 #include <asm/smp_plat.h>
0022 #include <asm-generic/mm_hooks.h>
0023
0024 void __check_vmalloc_seq(struct mm_struct *mm);
0025
0026 #ifdef CONFIG_MMU
0027 static inline void check_vmalloc_seq(struct mm_struct *mm)
0028 {
0029     if (!IS_ENABLED(CONFIG_ARM_LPAE) &&
0030         unlikely(atomic_read(&mm->context.vmalloc_seq) !=
0031              atomic_read(&init_mm.context.vmalloc_seq)))
0032         __check_vmalloc_seq(mm);
0033 }
0034 #endif
0035
0036 #ifdef CONFIG_CPU_HAS_ASID
0037
0038 void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
0039
0040 #define init_new_context init_new_context
0041 static inline int
0042 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
0043 {
0044     atomic64_set(&mm->context.id, 0);
0045     return 0;
0046 }
0047
0048 #ifdef CONFIG_ARM_ERRATA_798181
0049 void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
0050                  cpumask_t *mask);
0051 #else  /* !CONFIG_ARM_ERRATA_798181 */
0052 static inline void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
0053                        cpumask_t *mask)
0054 {
0055 }
0056 #endif /* CONFIG_ARM_ERRATA_798181 */
0057
0058 #else   /* !CONFIG_CPU_HAS_ASID */
0059
0060 #ifdef CONFIG_MMU
0061
0062 static inline void check_and_switch_context(struct mm_struct *mm,
0063                         struct task_struct *tsk)
0064 {
0065     check_vmalloc_seq(mm);
0066
0067     if (irqs_disabled())
0068         /*
0069          * cpu_switch_mm() needs to flush the VIVT caches. To avoid
0070          * high interrupt latencies, defer the call and continue
0071          * running with the old mm. Since we only support UP systems
0072          * on non-ASID CPUs, the old mm will remain valid until the
0073          * finish_arch_post_lock_switch() call.
0074          */
0075         mm->context.switch_pending = 1;
0076     else
0077         cpu_switch_mm(mm->pgd, mm);
0078 }
0079
0080 #ifndef MODULE
0081 #define finish_arch_post_lock_switch \
0082     finish_arch_post_lock_switch
0083 static inline void finish_arch_post_lock_switch(void)
0084 {
0085     struct mm_struct *mm = current->mm;
0086
0087     if (mm && mm->context.switch_pending) {
0088         /*
0089          * Preemption must be disabled during cpu_switch_mm() as we
0090          * have some stateful cache flush implementations. Check
0091          * switch_pending again in case we were preempted and the
0092          * switch to this mm was already done.
0093          */
0094         preempt_disable();
0095         if (mm->context.switch_pending) {
0096             mm->context.switch_pending = 0;
0097             cpu_switch_mm(mm->pgd, mm);
0098         }
0099         preempt_enable_no_resched();
0100     }
0101 }
0102 #endif /* !MODULE */
0103
0104 #endif  /* CONFIG_MMU */
0105
0106 #endif  /* CONFIG_CPU_HAS_ASID */
0107
0108 #define activate_mm(prev,next)      switch_mm(prev, next, NULL)
0109
0110 /*
0111  * This is the actual mm switch as far as the scheduler
0112  * is concerned.  No registers are touched.  We avoid
0113  * calling the CPU specific function when the mm hasn't
0114  * actually changed.
0115  */
0116 static inline void
0117 switch_mm(struct mm_struct *prev, struct mm_struct *next,
0118       struct task_struct *tsk)
0119 {
0120 #ifdef CONFIG_MMU
0121     unsigned int cpu = smp_processor_id();
0122
0123     /*
0124      * __sync_icache_dcache doesn't broadcast the I-cache invalidation,
0125      * so check for possible thread migration and invalidate the I-cache
0126      * if we're new to this CPU.
0127      */
0128     if (cache_ops_need_broadcast() &&
0129         !cpumask_empty(mm_cpumask(next)) &&
0130         !cpumask_test_cpu(cpu, mm_cpumask(next)))
0131         __flush_icache_all();
0132
0133     if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
0134         check_and_switch_context(next, tsk);
0135         if (cache_is_vivt())
0136             cpumask_clear_cpu(cpu, mm_cpumask(prev));
0137     }
0138 #endif
0139 }
0140
0141 #ifdef CONFIG_VMAP_STACK
0142 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
0143 {
0144     if (mm != &init_mm)
0145         check_vmalloc_seq(mm);
0146 }
0147 #define enter_lazy_tlb enter_lazy_tlb
0148 #endif
0149
0150 #include <asm-generic/mmu_context.h>
0151
0152 #endif