include/asm/hw_breakpoint.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ARM_HW_BREAKPOINT_H
0003 #define _ARM_HW_BREAKPOINT_H
0004
0005 #ifdef __KERNEL__
0006
0007 struct task_struct;
0008
0009 #ifdef CONFIG_HAVE_HW_BREAKPOINT
0010
0011 struct arch_hw_breakpoint_ctrl {
0012         u32 __reserved  : 9,
0013         mismatch    : 1,
0014                 : 9,
0015         len     : 8,
0016         type        : 2,
0017         privilege   : 2,
0018         enabled     : 1;
0019 };
0020
0021 struct arch_hw_breakpoint {
0022     u32 address;
0023     u32 trigger;
0024     struct  arch_hw_breakpoint_ctrl step_ctrl;
0025     struct  arch_hw_breakpoint_ctrl ctrl;
0026 };
0027
0028 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
0029 {
0030     return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
0031         (ctrl.privilege << 1) | ctrl.enabled;
0032 }
0033
0034 static inline void decode_ctrl_reg(u32 reg,
0035                    struct arch_hw_breakpoint_ctrl *ctrl)
0036 {
0037     ctrl->enabled   = reg & 0x1;
0038     reg >>= 1;
0039     ctrl->privilege = reg & 0x3;
0040     reg >>= 2;
0041     ctrl->type  = reg & 0x3;
0042     reg >>= 2;
0043     ctrl->len   = reg & 0xff;
0044     reg >>= 17;
0045     ctrl->mismatch  = reg & 0x1;
0046 }
0047
0048 /* Debug architecture numbers. */
0049 #define ARM_DEBUG_ARCH_RESERVED 0   /* In case of ptrace ABI updates. */
0050 #define ARM_DEBUG_ARCH_V6   1
0051 #define ARM_DEBUG_ARCH_V6_1 2
0052 #define ARM_DEBUG_ARCH_V7_ECP14 3
0053 #define ARM_DEBUG_ARCH_V7_MM    4
0054 #define ARM_DEBUG_ARCH_V7_1 5
0055 #define ARM_DEBUG_ARCH_V8   6
0056 #define ARM_DEBUG_ARCH_V8_1 7
0057 #define ARM_DEBUG_ARCH_V8_2 8
0058 #define ARM_DEBUG_ARCH_V8_4 9
0059
0060 /* Breakpoint */
0061 #define ARM_BREAKPOINT_EXECUTE  0
0062
0063 /* Watchpoints */
0064 #define ARM_BREAKPOINT_LOAD 1
0065 #define ARM_BREAKPOINT_STORE    2
0066 #define ARM_FSR_ACCESS_MASK (1 << 11)
0067
0068 /* Privilege Levels */
0069 #define ARM_BREAKPOINT_PRIV 1
0070 #define ARM_BREAKPOINT_USER 2
0071
0072 /* Lengths */
0073 #define ARM_BREAKPOINT_LEN_1    0x1
0074 #define ARM_BREAKPOINT_LEN_2    0x3
0075 #define ARM_BREAKPOINT_LEN_4    0xf
0076 #define ARM_BREAKPOINT_LEN_8    0xff
0077
0078 /* Limits */
0079 #define ARM_MAX_BRP     16
0080 #define ARM_MAX_WRP     16
0081 #define ARM_MAX_HBP_SLOTS   (ARM_MAX_BRP + ARM_MAX_WRP)
0082
0083 /* DSCR method of entry bits. */
0084 #define ARM_DSCR_MOE(x)         ((x >> 2) & 0xf)
0085 #define ARM_ENTRY_BREAKPOINT        0x1
0086 #define ARM_ENTRY_ASYNC_WATCHPOINT  0x2
0087 #define ARM_ENTRY_SYNC_WATCHPOINT   0xa
0088
0089 /* DSCR monitor/halting bits. */
0090 #define ARM_DSCR_HDBGEN     (1 << 14)
0091 #define ARM_DSCR_MDBGEN     (1 << 15)
0092
0093 /* OSLSR os lock model bits */
0094 #define ARM_OSLSR_OSLM0     (1 << 0)
0095
0096 /* opcode2 numbers for the co-processor instructions. */
0097 #define ARM_OP2_BVR     4
0098 #define ARM_OP2_BCR     5
0099 #define ARM_OP2_WVR     6
0100 #define ARM_OP2_WCR     7
0101
0102 /* Base register numbers for the debug registers. */
0103 #define ARM_BASE_BVR        64
0104 #define ARM_BASE_BCR        80
0105 #define ARM_BASE_WVR        96
0106 #define ARM_BASE_WCR        112
0107
0108 /* Accessor macros for the debug registers. */
0109 #define ARM_DBG_READ(N, M, OP2, VAL) do {\
0110     asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
0111 } while (0)
0112
0113 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
0114     asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
0115 } while (0)
0116
0117 struct perf_event_attr;
0118 struct notifier_block;
0119 struct perf_event;
0120 struct pmu;
0121
0122 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
0123                   int *gen_len, int *gen_type);
0124 extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
0125 extern int hw_breakpoint_arch_parse(struct perf_event *bp,
0126                     const struct perf_event_attr *attr,
0127                     struct arch_hw_breakpoint *hw);
0128 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
0129                        unsigned long val, void *data);
0130
0131 extern u8 arch_get_debug_arch(void);
0132 extern u8 arch_get_max_wp_len(void);
0133 extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
0134
0135 int arch_install_hw_breakpoint(struct perf_event *bp);
0136 void arch_uninstall_hw_breakpoint(struct perf_event *bp);
0137 void hw_breakpoint_pmu_read(struct perf_event *bp);
0138 int hw_breakpoint_slots(int type);
0139
0140 #else
0141 static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
0142
0143 #endif  /* CONFIG_HAVE_HW_BREAKPOINT */
0144 #endif  /* __KERNEL__ */
0145 #endif  /* _ARM_HW_BREAKPOINT_H */