asm/hardware/ioc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/include/asm/hardware/ioc.h
0004  *
0005  *  Copyright (C) Russell King
0006  *
0007  *  Use these macros to read/write the IOC.  All it does is perform the actual
0008  *  read/write.
0009  */
0010 #ifndef __ASMARM_HARDWARE_IOC_H
0011 #define __ASMARM_HARDWARE_IOC_H
0012
0013 #ifndef __ASSEMBLY__
0014
0015 /*
0016  * We use __raw_base variants here so that we give the compiler the
0017  * chance to keep IOC_BASE in a register.
0018  */
0019 #define ioc_readb(off)      __raw_readb(IOC_BASE + (off))
0020 #define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
0021
0022 #endif
0023
0024 #define IOC_CONTROL (0x00)
0025 #define IOC_KARTTX  (0x04)
0026 #define IOC_KARTRX  (0x04)
0027
0028 #define IOC_IRQSTATA    (0x10)
0029 #define IOC_IRQREQA (0x14)
0030 #define IOC_IRQCLRA (0x14)
0031 #define IOC_IRQMASKA    (0x18)
0032
0033 #define IOC_IRQSTATB    (0x20)
0034 #define IOC_IRQREQB (0x24)
0035 #define IOC_IRQMASKB    (0x28)
0036
0037 #define IOC_FIQSTAT (0x30)
0038 #define IOC_FIQREQ  (0x34)
0039 #define IOC_FIQMASK (0x38)
0040
0041 #define IOC_T0CNTL  (0x40)
0042 #define IOC_T0LTCHL (0x40)
0043 #define IOC_T0CNTH  (0x44)
0044 #define IOC_T0LTCHH (0x44)
0045 #define IOC_T0GO    (0x48)
0046 #define IOC_T0LATCH (0x4c)
0047
0048 #define IOC_T1CNTL  (0x50)
0049 #define IOC_T1LTCHL (0x50)
0050 #define IOC_T1CNTH  (0x54)
0051 #define IOC_T1LTCHH (0x54)
0052 #define IOC_T1GO    (0x58)
0053 #define IOC_T1LATCH (0x5c)
0054
0055 #define IOC_T2CNTL  (0x60)
0056 #define IOC_T2LTCHL (0x60)
0057 #define IOC_T2CNTH  (0x64)
0058 #define IOC_T2LTCHH (0x64)
0059 #define IOC_T2GO    (0x68)
0060 #define IOC_T2LATCH (0x6c)
0061
0062 #define IOC_T3CNTL  (0x70)
0063 #define IOC_T3LTCHL (0x70)
0064 #define IOC_T3CNTH  (0x74)
0065 #define IOC_T3LTCHH (0x74)
0066 #define IOC_T3GO    (0x78)
0067 #define IOC_T3LATCH (0x7c)
0068
0069 #endif