asm/hardware/dec21285.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/include/asm/hardware/dec21285.h
0004  *
0005  *  Copyright (C) 1998 Russell King
0006  *
0007  *  DC21285 registers
0008  */
0009 #define DC21285_PCI_IACK        0x79000000
0010 #define DC21285_ARMCSR_BASE     0x42000000
0011 #define DC21285_PCI_TYPE_0_CONFIG   0x7b000000
0012 #define DC21285_PCI_TYPE_1_CONFIG   0x7a000000
0013 #define DC21285_OUTBOUND_WRITE_FLUSH    0x78000000
0014 #define DC21285_FLASH           0x41000000
0015 #define DC21285_PCI_IO          0x7c000000
0016 #define DC21285_PCI_MEM         0x80000000
0017
0018 #ifndef __ASSEMBLY__
0019 #include <mach/hardware.h>
0020 #define DC21285_IO(x)       ((volatile unsigned long *)(ARMCSR_BASE+(x)))
0021 #else
0022 #define DC21285_IO(x)       (x)
0023 #endif
0024
0025 #define CSR_PCICMD      DC21285_IO(0x0004)
0026 #define CSR_CLASSREV        DC21285_IO(0x0008)
0027 #define CSR_PCICACHELINESIZE    DC21285_IO(0x000c)
0028 #define CSR_PCICSRBASE      DC21285_IO(0x0010)
0029 #define CSR_PCICSRIOBASE    DC21285_IO(0x0014)
0030 #define CSR_PCISDRAMBASE    DC21285_IO(0x0018)
0031 #define CSR_PCIROMBASE      DC21285_IO(0x0030)
0032 #define CSR_MBOX0       DC21285_IO(0x0050)
0033 #define CSR_MBOX1       DC21285_IO(0x0054)
0034 #define CSR_MBOX2       DC21285_IO(0x0058)
0035 #define CSR_MBOX3       DC21285_IO(0x005c)
0036 #define CSR_DOORBELL        DC21285_IO(0x0060)
0037 #define CSR_DOORBELL_SETUP  DC21285_IO(0x0064)
0038 #define CSR_ROMWRITEREG     DC21285_IO(0x0068)
0039 #define CSR_CSRBASEMASK     DC21285_IO(0x00f8)
0040 #define CSR_CSRBASEOFFSET   DC21285_IO(0x00fc)
0041 #define CSR_SDRAMBASEMASK   DC21285_IO(0x0100)
0042 #define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)
0043 #define CSR_ROMBASEMASK     DC21285_IO(0x0108)
0044 #define CSR_SDRAMTIMING     DC21285_IO(0x010c)
0045 #define CSR_SDRAMADDRSIZE0  DC21285_IO(0x0110)
0046 #define CSR_SDRAMADDRSIZE1  DC21285_IO(0x0114)
0047 #define CSR_SDRAMADDRSIZE2  DC21285_IO(0x0118)
0048 #define CSR_SDRAMADDRSIZE3  DC21285_IO(0x011c)
0049 #define CSR_I2O_INFREEHEAD  DC21285_IO(0x0120)
0050 #define CSR_I2O_INPOSTTAIL  DC21285_IO(0x0124)
0051 #define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)
0052 #define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)
0053 #define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)
0054 #define CSR_I2O_OUTPOSTCOUNT    DC21285_IO(0x0134)
0055 #define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)
0056 #define CSR_SA110_CNTL      DC21285_IO(0x013c)
0057 #define SA110_CNTL_INITCMPLETE      (1 << 0)
0058 #define SA110_CNTL_ASSERTSERR       (1 << 1)
0059 #define SA110_CNTL_RXSERR       (1 << 3)
0060 #define SA110_CNTL_SA110DRAMPARITY  (1 << 4)
0061 #define SA110_CNTL_PCISDRAMPARITY   (1 << 5)
0062 #define SA110_CNTL_DMASDRAMPARITY   (1 << 6)
0063 #define SA110_CNTL_DISCARDTIMER     (1 << 8)
0064 #define SA110_CNTL_PCINRESET        (1 << 9)
0065 #define SA110_CNTL_I2O_256      (0 << 10)
0066 #define SA110_CNTL_I20_512      (1 << 10)
0067 #define SA110_CNTL_I2O_1024     (2 << 10)
0068 #define SA110_CNTL_I2O_2048     (3 << 10)
0069 #define SA110_CNTL_I2O_4096     (4 << 10)
0070 #define SA110_CNTL_I2O_8192     (5 << 10)
0071 #define SA110_CNTL_I2O_16384        (6 << 10)
0072 #define SA110_CNTL_I2O_32768        (7 << 10)
0073 #define SA110_CNTL_WATCHDOG     (1 << 13)
0074 #define SA110_CNTL_ROMWIDTH_UNDEF   (0 << 14)
0075 #define SA110_CNTL_ROMWIDTH_16      (1 << 14)
0076 #define SA110_CNTL_ROMWIDTH_32      (2 << 14)
0077 #define SA110_CNTL_ROMWIDTH_8       (3 << 14)
0078 #define SA110_CNTL_ROMACCESSTIME(x) ((x)<<16)
0079 #define SA110_CNTL_ROMBURSTTIME(x)  ((x)<<20)
0080 #define SA110_CNTL_ROMTRISTATETIME(x)   ((x)<<24)
0081 #define SA110_CNTL_XCSDIR(x)        ((x)<<28)
0082 #define SA110_CNTL_PCICFN       (1 << 31)
0083
0084 /*
0085  * footbridge_cfn_mode() is used when we want
0086  * to check whether we are the central function
0087  */
0088 #define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)
0089 #if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN)
0090 #define footbridge_cfn_mode() __footbridge_cfn_mode()
0091 #elif defined(CONFIG_FOOTBRIDGE_HOST)
0092 #define footbridge_cfn_mode() (1)
0093 #else
0094 #define footbridge_cfn_mode() (0)
0095 #endif
0096
0097 #define CSR_PCIADDR_EXTN    DC21285_IO(0x0140)
0098 #define CSR_PREFETCHMEMRANGE    DC21285_IO(0x0144)
0099 #define CSR_XBUS_CYCLE      DC21285_IO(0x0148)
0100 #define CSR_XBUS_IOSTROBE   DC21285_IO(0x014c)
0101 #define CSR_DOORBELL_PCI    DC21285_IO(0x0150)
0102 #define CSR_DOORBELL_SA110  DC21285_IO(0x0154)
0103 #define CSR_UARTDR      DC21285_IO(0x0160)
0104 #define CSR_RXSTAT      DC21285_IO(0x0164)
0105 #define CSR_H_UBRLCR        DC21285_IO(0x0168)
0106 #define CSR_M_UBRLCR        DC21285_IO(0x016c)
0107 #define CSR_L_UBRLCR        DC21285_IO(0x0170)
0108 #define CSR_UARTCON     DC21285_IO(0x0174)
0109 #define CSR_UARTFLG     DC21285_IO(0x0178)
0110 #define CSR_IRQ_STATUS      DC21285_IO(0x0180)
0111 #define CSR_IRQ_RAWSTATUS   DC21285_IO(0x0184)
0112 #define CSR_IRQ_ENABLE      DC21285_IO(0x0188)
0113 #define CSR_IRQ_DISABLE     DC21285_IO(0x018c)
0114 #define CSR_IRQ_SOFT        DC21285_IO(0x0190)
0115 #define CSR_FIQ_STATUS      DC21285_IO(0x0280)
0116 #define CSR_FIQ_RAWSTATUS   DC21285_IO(0x0284)
0117 #define CSR_FIQ_ENABLE      DC21285_IO(0x0288)
0118 #define CSR_FIQ_DISABLE     DC21285_IO(0x028c)
0119 #define CSR_FIQ_SOFT        DC21285_IO(0x0290)
0120 #define CSR_TIMER1_LOAD     DC21285_IO(0x0300)
0121 #define CSR_TIMER1_VALUE    DC21285_IO(0x0304)
0122 #define CSR_TIMER1_CNTL     DC21285_IO(0x0308)
0123 #define CSR_TIMER1_CLR      DC21285_IO(0x030c)
0124 #define CSR_TIMER2_LOAD     DC21285_IO(0x0320)
0125 #define CSR_TIMER2_VALUE    DC21285_IO(0x0324)
0126 #define CSR_TIMER2_CNTL     DC21285_IO(0x0328)
0127 #define CSR_TIMER2_CLR      DC21285_IO(0x032c)
0128 #define CSR_TIMER3_LOAD     DC21285_IO(0x0340)
0129 #define CSR_TIMER3_VALUE    DC21285_IO(0x0344)
0130 #define CSR_TIMER3_CNTL     DC21285_IO(0x0348)
0131 #define CSR_TIMER3_CLR      DC21285_IO(0x034c)
0132 #define CSR_TIMER4_LOAD     DC21285_IO(0x0360)
0133 #define CSR_TIMER4_VALUE    DC21285_IO(0x0364)
0134 #define CSR_TIMER4_CNTL     DC21285_IO(0x0368)
0135 #define CSR_TIMER4_CLR      DC21285_IO(0x036c)
0136
0137 #define TIMER_CNTL_ENABLE   (1 << 7)
0138 #define TIMER_CNTL_AUTORELOAD   (1 << 6)
0139 #define TIMER_CNTL_DIV1     (0)
0140 #define TIMER_CNTL_DIV16    (1 << 2)
0141 #define TIMER_CNTL_DIV256   (2 << 2)
0142 #define TIMER_CNTL_CNTEXT   (3 << 2)
0143
0144