asm/hardware/cache-l2x0.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/include/asm/hardware/cache-l2x0.h
0004  *
0005  * Copyright (C) 2007 ARM Limited
0006  */
0007
0008 #ifndef __ASM_ARM_HARDWARE_L2X0_H
0009 #define __ASM_ARM_HARDWARE_L2X0_H
0010
0011 #include <linux/errno.h>
0012
0013 #define L2X0_CACHE_ID           0x000
0014 #define L2X0_CACHE_TYPE         0x004
0015 #define L2X0_CTRL           0x100
0016 #define L2X0_AUX_CTRL           0x104
0017 #define L310_TAG_LATENCY_CTRL       0x108
0018 #define L310_DATA_LATENCY_CTRL      0x10C
0019 #define L2X0_EVENT_CNT_CTRL     0x200
0020 #define L2X0_EVENT_CNT1_CFG     0x204
0021 #define L2X0_EVENT_CNT0_CFG     0x208
0022 #define L2X0_EVENT_CNT1_VAL     0x20C
0023 #define L2X0_EVENT_CNT0_VAL     0x210
0024 #define L2X0_INTR_MASK          0x214
0025 #define L2X0_MASKED_INTR_STAT       0x218
0026 #define L2X0_RAW_INTR_STAT      0x21C
0027 #define L2X0_INTR_CLEAR         0x220
0028 #define L2X0_CACHE_SYNC         0x730
0029 #define L2X0_DUMMY_REG          0x740
0030 #define L2X0_INV_LINE_PA        0x770
0031 #define L2X0_INV_WAY            0x77C
0032 #define L2X0_CLEAN_LINE_PA      0x7B0
0033 #define L2X0_CLEAN_LINE_IDX     0x7B8
0034 #define L2X0_CLEAN_WAY          0x7BC
0035 #define L2X0_CLEAN_INV_LINE_PA      0x7F0
0036 #define L2X0_CLEAN_INV_LINE_IDX     0x7F8
0037 #define L2X0_CLEAN_INV_WAY      0x7FC
0038 /*
0039  * The lockdown registers repeat 8 times for L310, the L210 has only one
0040  * D and one I lockdown register at 0x0900 and 0x0904.
0041  */
0042 #define L2X0_LOCKDOWN_WAY_D_BASE    0x900
0043 #define L2X0_LOCKDOWN_WAY_I_BASE    0x904
0044 #define L2X0_LOCKDOWN_STRIDE        0x08
0045 #define L310_ADDR_FILTER_START      0xC00
0046 #define L310_ADDR_FILTER_END        0xC04
0047 #define L2X0_TEST_OPERATION     0xF00
0048 #define L2X0_LINE_DATA          0xF10
0049 #define L2X0_LINE_TAG           0xF30
0050 #define L2X0_DEBUG_CTRL         0xF40
0051 #define L310_PREFETCH_CTRL      0xF60
0052 #define L310_POWER_CTRL         0xF80
0053 #define   L310_DYNAMIC_CLK_GATING_EN    (1 << 1)
0054 #define   L310_STNDBY_MODE_EN       (1 << 0)
0055
0056 /* Registers shifts and masks */
0057 #define L2X0_CACHE_ID_PART_MASK     (0xf << 6)
0058 #define L2X0_CACHE_ID_PART_L210     (1 << 6)
0059 #define L2X0_CACHE_ID_PART_L220     (2 << 6)
0060 #define L2X0_CACHE_ID_PART_L310     (3 << 6)
0061 #define L2X0_CACHE_ID_RTL_MASK          0x3f
0062 #define L210_CACHE_ID_RTL_R0P2_02   0x00
0063 #define L210_CACHE_ID_RTL_R0P1      0x01
0064 #define L210_CACHE_ID_RTL_R0P2_01   0x02
0065 #define L210_CACHE_ID_RTL_R0P3      0x03
0066 #define L210_CACHE_ID_RTL_R0P4      0x0b
0067 #define L210_CACHE_ID_RTL_R0P5      0x0f
0068 #define L220_CACHE_ID_RTL_R1P7_01REL0   0x06
0069 #define L310_CACHE_ID_RTL_R0P0      0x00
0070 #define L310_CACHE_ID_RTL_R1P0      0x02
0071 #define L310_CACHE_ID_RTL_R2P0      0x04
0072 #define L310_CACHE_ID_RTL_R3P0      0x05
0073 #define L310_CACHE_ID_RTL_R3P1      0x06
0074 #define L310_CACHE_ID_RTL_R3P1_50REL0   0x07
0075 #define L310_CACHE_ID_RTL_R3P2      0x08
0076 #define L310_CACHE_ID_RTL_R3P3      0x09
0077
0078 #define L2X0_EVENT_CNT_CTRL_ENABLE  BIT(0)
0079
0080 #define L2X0_EVENT_CNT_CFG_SRC_SHIFT    2
0081 #define L2X0_EVENT_CNT_CFG_SRC_MASK 0xf
0082 #define L2X0_EVENT_CNT_CFG_SRC_DISABLED 0
0083 #define L2X0_EVENT_CNT_CFG_INT_DISABLED 0
0084 #define L2X0_EVENT_CNT_CFG_INT_INCR 1
0085 #define L2X0_EVENT_CNT_CFG_INT_OVERFLOW 2
0086
0087 /* L2C auxiliary control register - bits common to L2C-210/220/310 */
0088 #define L2C_AUX_CTRL_WAY_SIZE_SHIFT     17
0089 #define L2C_AUX_CTRL_WAY_SIZE_MASK      (7 << 17)
0090 #define L2C_AUX_CTRL_WAY_SIZE(n)        ((n) << 17)
0091 #define L2C_AUX_CTRL_EVTMON_ENABLE      BIT(20)
0092 #define L2C_AUX_CTRL_PARITY_ENABLE      BIT(21)
0093 #define L2C_AUX_CTRL_SHARED_OVERRIDE        BIT(22)
0094 /* L2C-210/220 common bits */
0095 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
0096 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK  (7 << 0)
0097 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
0098 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK  (7 << 3)
0099 #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT     6
0100 #define L2X0_AUX_CTRL_TAG_LATENCY_MASK      (7 << 6)
0101 #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT   9
0102 #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK    (7 << 9)
0103 #define L2X0_AUX_CTRL_ASSOC_SHIFT       13
0104 #define L2X0_AUX_CTRL_ASSOC_MASK        (15 << 13)
0105 /* L2C-210 specific bits */
0106 #define L210_AUX_CTRL_WRAP_DISABLE      BIT(12)
0107 #define L210_AUX_CTRL_WA_OVERRIDE       BIT(23)
0108 #define L210_AUX_CTRL_EXCLUSIVE_ABORT       BIT(24)
0109 /* L2C-220 specific bits */
0110 #define L220_AUX_CTRL_EXCLUSIVE_CACHE       BIT(12)
0111 #define L220_AUX_CTRL_FWA_SHIFT         23
0112 #define L220_AUX_CTRL_FWA_MASK          (3 << 23)
0113 #define L220_AUX_CTRL_NS_LOCKDOWN       BIT(26)
0114 #define L220_AUX_CTRL_NS_INT_CTRL       BIT(27)
0115 /* L2C-310 specific bits */
0116 #define L310_AUX_CTRL_FULL_LINE_ZERO        BIT(0)  /* R2P0+ */
0117 #define L310_AUX_CTRL_HIGHPRIO_SO_DEV       BIT(10) /* R2P0+ */
0118 #define L310_AUX_CTRL_STORE_LIMITATION      BIT(11) /* R2P0+ */
0119 #define L310_AUX_CTRL_EXCLUSIVE_CACHE       BIT(12)
0120 #define L310_AUX_CTRL_ASSOCIATIVITY_16      BIT(16)
0121 #define L310_AUX_CTRL_FWA_SHIFT         23
0122 #define L310_AUX_CTRL_FWA_MASK          (3 << 23)
0123 #define L310_AUX_CTRL_CACHE_REPLACE_RR      BIT(25) /* R2P0+ */
0124 #define L310_AUX_CTRL_NS_LOCKDOWN       BIT(26)
0125 #define L310_AUX_CTRL_NS_INT_CTRL       BIT(27)
0126 #define L310_AUX_CTRL_DATA_PREFETCH     BIT(28)
0127 #define L310_AUX_CTRL_INSTR_PREFETCH        BIT(29)
0128 #define L310_AUX_CTRL_EARLY_BRESP       BIT(30) /* R2P0+ */
0129
0130 #define L310_LATENCY_CTRL_SETUP(n)      ((n) << 0)
0131 #define L310_LATENCY_CTRL_RD(n)         ((n) << 4)
0132 #define L310_LATENCY_CTRL_WR(n)         ((n) << 8)
0133
0134 #define L310_ADDR_FILTER_EN     1
0135
0136 #define L310_PREFETCH_CTRL_OFFSET_MASK      0x1f
0137 #define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR    BIT(23)
0138 #define L310_PREFETCH_CTRL_PREFETCH_DROP    BIT(24)
0139 #define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP    BIT(27)
0140 #define L310_PREFETCH_CTRL_DATA_PREFETCH    BIT(28)
0141 #define L310_PREFETCH_CTRL_INSTR_PREFETCH   BIT(29)
0142 #define L310_PREFETCH_CTRL_DBL_LINEFILL     BIT(30)
0143
0144 #define L2X0_CTRL_EN            1
0145
0146 #define L2X0_WAY_SIZE_SHIFT     3
0147
0148 #ifndef __ASSEMBLY__
0149 extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
0150 #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
0151 extern int l2x0_of_init(u32 aux_val, u32 aux_mask);
0152 #else
0153 static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
0154 {
0155     return -ENODEV;
0156 }
0157 #endif
0158
0159 #ifdef CONFIG_CACHE_L2X0_PMU
0160 void l2x0_pmu_register(void __iomem *base, u32 part);
0161 void l2x0_pmu_suspend(void);
0162 void l2x0_pmu_resume(void);
0163 #else
0164 static inline void l2x0_pmu_register(void __iomem *base, u32 part) {}
0165 static inline void l2x0_pmu_suspend(void) {}
0166 static inline void l2x0_pmu_resume(void) {}
0167 #endif
0168
0169 struct l2x0_regs {
0170     unsigned long phy_base;
0171     unsigned long aux_ctrl;
0172     /*
0173      * Whether the following registers need to be saved/restored
0174      * depends on platform
0175      */
0176     unsigned long tag_latency;
0177     unsigned long data_latency;
0178     unsigned long filter_start;
0179     unsigned long filter_end;
0180     unsigned long prefetch_ctrl;
0181     unsigned long pwr_ctrl;
0182     unsigned long ctrl;
0183     unsigned long aux2_ctrl;
0184 };
0185
0186 extern struct l2x0_regs l2x0_saved_regs;
0187
0188 #endif /* __ASSEMBLY__ */
0189
0190 #endif