asm/hardware/cache-aurora-l2.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * AURORA shared L2 cache controller support
0004  *
0005  * Copyright (C) 2012 Marvell
0006  *
0007  * Yehuda Yitschak <yehuday@marvell.com>
0008  * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009  */
0010
0011 #ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
0012 #define __ASM_ARM_HARDWARE_AURORA_L2_H
0013
0014 #define AURORA_SYNC_REG         0x700
0015 #define AURORA_RANGE_BASE_ADDR_REG  0x720
0016 #define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
0017 #define AURORA_INVAL_RANGE_REG      0x774
0018 #define AURORA_CLEAN_RANGE_REG      0x7b4
0019 #define AURORA_FLUSH_RANGE_REG      0x7f4
0020
0021 #define AURORA_ACR_REPLACEMENT_OFFSET       27
0022 #define AURORA_ACR_REPLACEMENT_MASK      \
0023     (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
0024 #define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
0025     (0 << AURORA_ACR_REPLACEMENT_OFFSET)
0026 #define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
0027     (1 << AURORA_ACR_REPLACEMENT_OFFSET)
0028 #define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
0029     (3 << AURORA_ACR_REPLACEMENT_OFFSET)
0030
0031 #define AURORA_ACR_PARITY_EN    (1 << 21)
0032 #define AURORA_ACR_ECC_EN   (1 << 20)
0033
0034 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET    0
0035 #define AURORA_ACR_FORCE_WRITE_POLICY_MASK  \
0036     (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
0037 #define AURORA_ACR_FORCE_WRITE_POLICY_DIS   \
0038     (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
0039 #define AURORA_ACR_FORCE_WRITE_BACK_POLICY  \
0040     (1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
0041 #define AURORA_ACR_FORCE_WRITE_THRO_POLICY  \
0042     (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
0043
0044 #define AURORA_ERR_CNT_REG          0x600
0045 #define AURORA_ERR_ATTR_CAP_REG     0x608
0046 #define AURORA_ERR_ADDR_CAP_REG     0x60c
0047 #define AURORA_ERR_WAY_CAP_REG      0x610
0048 #define AURORA_ERR_INJECT_CTL_REG   0x614
0049 #define AURORA_ERR_INJECT_MASK_REG  0x618
0050
0051 #define AURORA_ERR_CNT_CLR_OFFSET         31
0052 #define AURORA_ERR_CNT_CLR         \
0053     (0x1 << AURORA_ERR_CNT_CLR_OFFSET)
0054 #define AURORA_ERR_CNT_UE_OFFSET          16
0055 #define AURORA_ERR_CNT_UE_MASK             \
0056     (0x7fff << AURORA_ERR_CNT_UE_OFFSET)
0057 #define AURORA_ERR_CNT_CE_OFFSET           0
0058 #define AURORA_ERR_CNT_CE_MASK             \
0059     (0xffff << AURORA_ERR_CNT_CE_OFFSET)
0060
0061 #define AURORA_ERR_ATTR_SRC_OFF           16
0062 #define AURORA_ERR_ATTR_SRC_MSK            \
0063     (0x7 << AURORA_ERR_ATTR_SRC_OFF)
0064 #define AURORA_ERR_ATTR_TXN_OFF           12
0065 #define AURORA_ERR_ATTR_TXN_MSK            \
0066     (0xf << AURORA_ERR_ATTR_TXN_OFF)
0067 #define AURORA_ERR_ATTR_ERR_OFF            8
0068 #define AURORA_ERR_ATTR_ERR_MSK            \
0069     (0x3 << AURORA_ERR_ATTR_ERR_OFF)
0070 #define AURORA_ERR_ATTR_CAP_VALID_OFF      0
0071 #define AURORA_ERR_ATTR_CAP_VALID          \
0072     (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF)
0073
0074 #define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0
0075
0076 #define AURORA_ERR_WAY_IDX_OFF             8
0077 #define AURORA_ERR_WAY_IDX_MSK             \
0078     (0xfff << AURORA_ERR_WAY_IDX_OFF)
0079 #define AURORA_ERR_WAY_CAP_WAY_OFFSET      1
0080 #define AURORA_ERR_WAY_CAP_WAY_MASK        \
0081     (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET)
0082
0083 #define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0
0084 #define AURORA_ERR_ATTR_TXN_OFF   12
0085 #define AURORA_ERR_INJECT_CTL_EN_MASK          0x3
0086 #define AURORA_ERR_INJECT_CTL_EN_PARITY        0x2
0087 #define AURORA_ERR_INJECT_CTL_EN_ECC           0x1
0088
0089 #define AURORA_MAX_RANGE_SIZE   1024
0090
0091 #define AURORA_WAY_SIZE_SHIFT   2
0092
0093 #define AURORA_CTRL_FW      0x100
0094
0095 /* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
0096  * the distinction between a number coming from hardware and a number
0097  * coming from the device tree */
0098 #define AURORA_CACHE_ID        0x100
0099
0100 #endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */