include/asm/glue-cache.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  arch/arm/include/asm/glue-cache.h
0004  *
0005  *  Copyright (C) 1999-2002 Russell King
0006  */
0007 #ifndef ASM_GLUE_CACHE_H
0008 #define ASM_GLUE_CACHE_H
0009
0010 #include <asm/glue.h>
0011
0012 /*
0013  *  Cache Model
0014  *  ===========
0015  */
0016 #undef _CACHE
0017 #undef MULTI_CACHE
0018
0019 #if defined(CONFIG_CPU_CACHE_V4)
0020 # ifdef _CACHE
0021 #  define MULTI_CACHE 1
0022 # else
0023 #  define _CACHE v4
0024 # endif
0025 #endif
0026
0027 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
0028     defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
0029     defined(CONFIG_CPU_ARM1026)
0030 # define MULTI_CACHE 1
0031 #endif
0032
0033 #if defined(CONFIG_CPU_FA526)
0034 # ifdef _CACHE
0035 #  define MULTI_CACHE 1
0036 # else
0037 #  define _CACHE fa
0038 # endif
0039 #endif
0040
0041 #if defined(CONFIG_CPU_ARM926T)
0042 # ifdef _CACHE
0043 #  define MULTI_CACHE 1
0044 # else
0045 #  define _CACHE arm926
0046 # endif
0047 #endif
0048
0049 #if defined(CONFIG_CPU_ARM940T)
0050 # ifdef _CACHE
0051 #  define MULTI_CACHE 1
0052 # else
0053 #  define _CACHE arm940
0054 # endif
0055 #endif
0056
0057 #if defined(CONFIG_CPU_ARM946E)
0058 # ifdef _CACHE
0059 #  define MULTI_CACHE 1
0060 # else
0061 #  define _CACHE arm946
0062 # endif
0063 #endif
0064
0065 #if defined(CONFIG_CPU_CACHE_V4WB)
0066 # ifdef _CACHE
0067 #  define MULTI_CACHE 1
0068 # else
0069 #  define _CACHE v4wb
0070 # endif
0071 #endif
0072
0073 #if defined(CONFIG_CPU_XSCALE)
0074 # ifdef _CACHE
0075 #  define MULTI_CACHE 1
0076 # else
0077 #  define _CACHE xscale
0078 # endif
0079 #endif
0080
0081 #if defined(CONFIG_CPU_XSC3)
0082 # ifdef _CACHE
0083 #  define MULTI_CACHE 1
0084 # else
0085 #  define _CACHE xsc3
0086 # endif
0087 #endif
0088
0089 #if defined(CONFIG_CPU_MOHAWK)
0090 # ifdef _CACHE
0091 #  define MULTI_CACHE 1
0092 # else
0093 #  define _CACHE mohawk
0094 # endif
0095 #endif
0096
0097 #if defined(CONFIG_CPU_FEROCEON)
0098 # define MULTI_CACHE 1
0099 #endif
0100
0101 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
0102 # ifdef _CACHE
0103 #  define MULTI_CACHE 1
0104 # else
0105 #  define _CACHE v6
0106 # endif
0107 #endif
0108
0109 #if defined(CONFIG_CPU_V7)
0110 # ifdef _CACHE
0111 #  define MULTI_CACHE 1
0112 # else
0113 #  define _CACHE v7
0114 # endif
0115 #endif
0116
0117 #if defined(CONFIG_CACHE_B15_RAC)
0118 # define MULTI_CACHE 1
0119 #endif
0120
0121 #if defined(CONFIG_CPU_V7M)
0122 #  define MULTI_CACHE 1
0123 #endif
0124
0125 #if !defined(_CACHE) && !defined(MULTI_CACHE)
0126 #error Unknown cache maintenance model
0127 #endif
0128
0129 #ifndef __ASSEMBLER__
0130 static inline void nop_flush_icache_all(void) { }
0131 static inline void nop_flush_kern_cache_all(void) { }
0132 static inline void nop_flush_kern_cache_louis(void) { }
0133 static inline void nop_flush_user_cache_all(void) { }
0134 static inline void nop_flush_user_cache_range(unsigned long a,
0135         unsigned long b, unsigned int c) { }
0136
0137 static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
0138 static inline int nop_coherent_user_range(unsigned long a,
0139         unsigned long b) { return 0; }
0140 static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
0141
0142 static inline void nop_dma_flush_range(const void *a, const void *b) { }
0143
0144 static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
0145 static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
0146 #endif
0147
0148 #ifndef MULTI_CACHE
0149 #define __cpuc_flush_icache_all     __glue(_CACHE,_flush_icache_all)
0150 #define __cpuc_flush_kern_all       __glue(_CACHE,_flush_kern_cache_all)
0151 #define __cpuc_flush_kern_louis     __glue(_CACHE,_flush_kern_cache_louis)
0152 #define __cpuc_flush_user_all       __glue(_CACHE,_flush_user_cache_all)
0153 #define __cpuc_flush_user_range     __glue(_CACHE,_flush_user_cache_range)
0154 #define __cpuc_coherent_kern_range  __glue(_CACHE,_coherent_kern_range)
0155 #define __cpuc_coherent_user_range  __glue(_CACHE,_coherent_user_range)
0156 #define __cpuc_flush_dcache_area    __glue(_CACHE,_flush_kern_dcache_area)
0157
0158 #define dmac_flush_range        __glue(_CACHE,_dma_flush_range)
0159 #endif
0160
0161 #endif