include/asm/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_ARM_DMA_H
0003 #define __ASM_ARM_DMA_H
0004
0005 /*
0006  * This is the maximum virtual address which can be DMA'd from.
0007  */
0008 #ifndef CONFIG_ZONE_DMA
0009 #define MAX_DMA_ADDRESS 0xffffffffUL
0010 #else
0011 #define MAX_DMA_ADDRESS ({ \
0012     extern phys_addr_t arm_dma_zone_size; \
0013     arm_dma_zone_size && arm_dma_zone_size < (0x100000000ULL - PAGE_OFFSET) ? \
0014         (PAGE_OFFSET + arm_dma_zone_size) : 0xffffffffUL; })
0015 #endif
0016
0017 #ifdef CONFIG_ISA_DMA_API
0018 /*
0019  * This is used to support drivers written for the x86 ISA DMA API.
0020  * It should not be re-used except for that purpose.
0021  */
0022 #include <linux/spinlock.h>
0023 #include <linux/scatterlist.h>
0024
0025 #include <mach/isa-dma.h>
0026
0027 /*
0028  * The DMA modes reflect the settings for the ISA DMA controller
0029  */
0030 #define DMA_MODE_MASK    0xcc
0031
0032 #define DMA_MODE_READ    0x44
0033 #define DMA_MODE_WRITE   0x48
0034 #define DMA_MODE_CASCADE 0xc0
0035 #define DMA_AUTOINIT     0x10
0036
0037 extern raw_spinlock_t  dma_spin_lock;
0038
0039 static inline unsigned long claim_dma_lock(void)
0040 {
0041     unsigned long flags;
0042     raw_spin_lock_irqsave(&dma_spin_lock, flags);
0043     return flags;
0044 }
0045
0046 static inline void release_dma_lock(unsigned long flags)
0047 {
0048     raw_spin_unlock_irqrestore(&dma_spin_lock, flags);
0049 }
0050
0051 /* Clear the 'DMA Pointer Flip Flop'.
0052  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
0053  */
0054 #define clear_dma_ff(chan)
0055
0056 /* Set only the page register bits of the transfer address.
0057  *
0058  * NOTE: This is an architecture specific function, and should
0059  *       be hidden from the drivers
0060  */
0061 extern void set_dma_page(unsigned int chan, char pagenr);
0062
0063 /* Request a DMA channel
0064  *
0065  * Some architectures may need to do allocate an interrupt
0066  */
0067 extern int  request_dma(unsigned int chan, const char * device_id);
0068
0069 /* Free a DMA channel
0070  *
0071  * Some architectures may need to do free an interrupt
0072  */
0073 extern void free_dma(unsigned int chan);
0074
0075 /* Enable DMA for this channel
0076  *
0077  * On some architectures, this may have other side effects like
0078  * enabling an interrupt and setting the DMA registers.
0079  */
0080 extern void enable_dma(unsigned int chan);
0081
0082 /* Disable DMA for this channel
0083  *
0084  * On some architectures, this may have other side effects like
0085  * disabling an interrupt or whatever.
0086  */
0087 extern void disable_dma(unsigned int chan);
0088
0089 /* Test whether the specified channel has an active DMA transfer
0090  */
0091 extern int dma_channel_active(unsigned int chan);
0092
0093 /* Set the DMA scatter gather list for this channel
0094  *
0095  * This should not be called if a DMA channel is enabled,
0096  * especially since some DMA architectures don't update the
0097  * DMA address immediately, but defer it to the enable_dma().
0098  */
0099 extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg);
0100
0101 /* Set the DMA address for this channel
0102  *
0103  * This should not be called if a DMA channel is enabled,
0104  * especially since some DMA architectures don't update the
0105  * DMA address immediately, but defer it to the enable_dma().
0106  */
0107 extern void __set_dma_addr(unsigned int chan, void *addr);
0108 #define set_dma_addr(chan, addr)                \
0109     __set_dma_addr(chan, (void *)__bus_to_virt(addr))
0110
0111 /* Set the DMA byte count for this channel
0112  *
0113  * This should not be called if a DMA channel is enabled,
0114  * especially since some DMA architectures don't update the
0115  * DMA count immediately, but defer it to the enable_dma().
0116  */
0117 extern void set_dma_count(unsigned int chan, unsigned long count);
0118
0119 /* Set the transfer direction for this channel
0120  *
0121  * This should not be called if a DMA channel is enabled,
0122  * especially since some DMA architectures don't update the
0123  * DMA transfer direction immediately, but defer it to the
0124  * enable_dma().
0125  */
0126 extern void set_dma_mode(unsigned int chan, unsigned int mode);
0127
0128 /* Set the transfer speed for this channel
0129  */
0130 extern void set_dma_speed(unsigned int chan, int cycle_ns);
0131
0132 /* Get DMA residue count. After a DMA transfer, this
0133  * should return zero. Reading this while a DMA transfer is
0134  * still in progress will return unpredictable results.
0135  * If called before the channel has been used, it may return 1.
0136  * Otherwise, it returns the number of _bytes_ left to transfer.
0137  */
0138 extern int  get_dma_residue(unsigned int chan);
0139
0140 #ifndef NO_DMA
0141 #define NO_DMA  255
0142 #endif
0143
0144 #endif /* CONFIG_ISA_DMA_API */
0145
0146 #endif /* __ASM_ARM_DMA_H */