include/asm/cti.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASMARM_CTI_H
0003 #define __ASMARM_CTI_H
0004
0005 #include    <asm/io.h>
0006 #include    <asm/hardware/coresight.h>
0007
0008 /* The registers' definition is from section 3.2 of
0009  * Embedded Cross Trigger Revision: r0p0
0010  */
0011 #define     CTICONTROL      0x000
0012 #define     CTISTATUS       0x004
0013 #define     CTILOCK         0x008
0014 #define     CTIPROTECTION       0x00C
0015 #define     CTIINTACK       0x010
0016 #define     CTIAPPSET       0x014
0017 #define     CTIAPPCLEAR     0x018
0018 #define     CTIAPPPULSE     0x01c
0019 #define     CTIINEN         0x020
0020 #define     CTIOUTEN        0x0A0
0021 #define     CTITRIGINSTATUS     0x130
0022 #define     CTITRIGOUTSTATUS    0x134
0023 #define     CTICHINSTATUS       0x138
0024 #define     CTICHOUTSTATUS      0x13c
0025 #define     CTIPERIPHID0        0xFE0
0026 #define     CTIPERIPHID1        0xFE4
0027 #define     CTIPERIPHID2        0xFE8
0028 #define     CTIPERIPHID3        0xFEC
0029 #define     CTIPCELLID0     0xFF0
0030 #define     CTIPCELLID1     0xFF4
0031 #define     CTIPCELLID2     0xFF8
0032 #define     CTIPCELLID3     0xFFC
0033
0034 /* The below are from section 3.6.4 of
0035  * CoreSight v1.0 Architecture Specification
0036  */
0037 #define     LOCKACCESS      0xFB0
0038 #define     LOCKSTATUS      0xFB4
0039
0040 /**
0041  * struct cti - cross trigger interface struct
0042  * @base: mapped virtual address for the cti base
0043  * @irq: irq number for the cti
0044  * @trig_out_for_irq: triger out number which will cause
0045  *  the @irq happen
0046  *
0047  * cti struct used to operate cti registers.
0048  */
0049 struct cti {
0050     void __iomem *base;
0051     int irq;
0052     int trig_out_for_irq;
0053 };
0054
0055 /**
0056  * cti_init - initialize the cti instance
0057  * @cti: cti instance
0058  * @base: mapped virtual address for the cti base
0059  * @irq: irq number for the cti
0060  * @trig_out: triger out number which will cause
0061  *  the @irq happen
0062  *
0063  * called by machine code to pass the board dependent
0064  * @base, @irq and @trig_out to cti.
0065  */
0066 static inline void cti_init(struct cti *cti,
0067     void __iomem *base, int irq, int trig_out)
0068 {
0069     cti->base = base;
0070     cti->irq  = irq;
0071     cti->trig_out_for_irq = trig_out;
0072 }
0073
0074 /**
0075  * cti_map_trigger - use the @chan to map @trig_in to @trig_out
0076  * @cti: cti instance
0077  * @trig_in: trigger in number
0078  * @trig_out: trigger out number
0079  * @channel: channel number
0080  *
0081  * This function maps one trigger in of @trig_in to one trigger
0082  * out of @trig_out using the channel @chan.
0083  */
0084 static inline void cti_map_trigger(struct cti *cti,
0085     int trig_in, int trig_out, int chan)
0086 {
0087     void __iomem *base = cti->base;
0088     unsigned long val;
0089
0090     val = __raw_readl(base + CTIINEN + trig_in * 4);
0091     val |= BIT(chan);
0092     __raw_writel(val, base + CTIINEN + trig_in * 4);
0093
0094     val = __raw_readl(base + CTIOUTEN + trig_out * 4);
0095     val |= BIT(chan);
0096     __raw_writel(val, base + CTIOUTEN + trig_out * 4);
0097 }
0098
0099 /**
0100  * cti_enable - enable the cti module
0101  * @cti: cti instance
0102  *
0103  * enable the cti module
0104  */
0105 static inline void cti_enable(struct cti *cti)
0106 {
0107     __raw_writel(0x1, cti->base + CTICONTROL);
0108 }
0109
0110 /**
0111  * cti_disable - disable the cti module
0112  * @cti: cti instance
0113  *
0114  * enable the cti module
0115  */
0116 static inline void cti_disable(struct cti *cti)
0117 {
0118     __raw_writel(0, cti->base + CTICONTROL);
0119 }
0120
0121 /**
0122  * cti_irq_ack - clear the cti irq
0123  * @cti: cti instance
0124  *
0125  * clear the cti irq
0126  */
0127 static inline void cti_irq_ack(struct cti *cti)
0128 {
0129     void __iomem *base = cti->base;
0130     unsigned long val;
0131
0132     val = __raw_readl(base + CTIINTACK);
0133     val |= BIT(cti->trig_out_for_irq);
0134     __raw_writel(val, base + CTIINTACK);
0135 }
0136
0137 /**
0138  * cti_unlock - unlock cti module
0139  * @cti: cti instance
0140  *
0141  * unlock the cti module, or else any writes to the cti
0142  * module is not allowed.
0143  */
0144 static inline void cti_unlock(struct cti *cti)
0145 {
0146     __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
0147 }
0148
0149 /**
0150  * cti_lock - lock cti module
0151  * @cti: cti instance
0152  *
0153  * lock the cti module, so any writes to the cti
0154  * module will be not allowed.
0155  */
0156 static inline void cti_lock(struct cti *cti)
0157 {
0158     __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
0159 }
0160 #endif