include/asm/cputype.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_ARM_CPUTYPE_H
0003 #define __ASM_ARM_CPUTYPE_H
0004
0005 #define CPUID_ID    0
0006 #define CPUID_CACHETYPE 1
0007 #define CPUID_TCM   2
0008 #define CPUID_TLBTYPE   3
0009 #define CPUID_MPUIR 4
0010 #define CPUID_MPIDR 5
0011 #define CPUID_REVIDR    6
0012
0013 #ifdef CONFIG_CPU_V7M
0014 #define CPUID_EXT_PFR0  0x40
0015 #define CPUID_EXT_PFR1  0x44
0016 #define CPUID_EXT_DFR0  0x48
0017 #define CPUID_EXT_AFR0  0x4c
0018 #define CPUID_EXT_MMFR0 0x50
0019 #define CPUID_EXT_MMFR1 0x54
0020 #define CPUID_EXT_MMFR2 0x58
0021 #define CPUID_EXT_MMFR3 0x5c
0022 #define CPUID_EXT_ISAR0 0x60
0023 #define CPUID_EXT_ISAR1 0x64
0024 #define CPUID_EXT_ISAR2 0x68
0025 #define CPUID_EXT_ISAR3 0x6c
0026 #define CPUID_EXT_ISAR4 0x70
0027 #define CPUID_EXT_ISAR5 0x74
0028 #else
0029 #define CPUID_EXT_PFR0  "c1, 0"
0030 #define CPUID_EXT_PFR1  "c1, 1"
0031 #define CPUID_EXT_DFR0  "c1, 2"
0032 #define CPUID_EXT_AFR0  "c1, 3"
0033 #define CPUID_EXT_MMFR0 "c1, 4"
0034 #define CPUID_EXT_MMFR1 "c1, 5"
0035 #define CPUID_EXT_MMFR2 "c1, 6"
0036 #define CPUID_EXT_MMFR3 "c1, 7"
0037 #define CPUID_EXT_ISAR0 "c2, 0"
0038 #define CPUID_EXT_ISAR1 "c2, 1"
0039 #define CPUID_EXT_ISAR2 "c2, 2"
0040 #define CPUID_EXT_ISAR3 "c2, 3"
0041 #define CPUID_EXT_ISAR4 "c2, 4"
0042 #define CPUID_EXT_ISAR5 "c2, 5"
0043 #endif
0044
0045 #define MPIDR_SMP_BITMASK (0x3 << 30)
0046 #define MPIDR_SMP_VALUE (0x2 << 30)
0047
0048 #define MPIDR_MT_BITMASK (0x1 << 24)
0049
0050 #define MPIDR_HWID_BITMASK 0xFFFFFF
0051
0052 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
0053
0054 #define MPIDR_LEVEL_BITS 8
0055 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
0056 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
0057
0058 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
0059     ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
0060
0061 #define ARM_CPU_IMP_ARM         0x41
0062 #define ARM_CPU_IMP_BRCM        0x42
0063 #define ARM_CPU_IMP_DEC         0x44
0064 #define ARM_CPU_IMP_INTEL       0x69
0065
0066 /* ARM implemented processors */
0067 #define ARM_CPU_PART_ARM1136        0x4100b360
0068 #define ARM_CPU_PART_ARM1156        0x4100b560
0069 #define ARM_CPU_PART_ARM1176        0x4100b760
0070 #define ARM_CPU_PART_ARM11MPCORE    0x4100b020
0071 #define ARM_CPU_PART_CORTEX_A8      0x4100c080
0072 #define ARM_CPU_PART_CORTEX_A9      0x4100c090
0073 #define ARM_CPU_PART_CORTEX_A5      0x4100c050
0074 #define ARM_CPU_PART_CORTEX_A7      0x4100c070
0075 #define ARM_CPU_PART_CORTEX_A12     0x4100c0d0
0076 #define ARM_CPU_PART_CORTEX_A17     0x4100c0e0
0077 #define ARM_CPU_PART_CORTEX_A15     0x4100c0f0
0078 #define ARM_CPU_PART_CORTEX_A53     0x4100d030
0079 #define ARM_CPU_PART_CORTEX_A57     0x4100d070
0080 #define ARM_CPU_PART_CORTEX_A72     0x4100d080
0081 #define ARM_CPU_PART_CORTEX_A73     0x4100d090
0082 #define ARM_CPU_PART_CORTEX_A75     0x4100d0a0
0083 #define ARM_CPU_PART_MASK       0xff00fff0
0084
0085 /* Broadcom implemented processors */
0086 #define ARM_CPU_PART_BRAHMA_B15     0x420000f0
0087 #define ARM_CPU_PART_BRAHMA_B53     0x42001000
0088
0089 /* DEC implemented cores */
0090 #define ARM_CPU_PART_SA1100     0x4400a110
0091
0092 /* Intel implemented cores */
0093 #define ARM_CPU_PART_SA1110     0x6900b110
0094 #define ARM_CPU_REV_SA1110_A0       0
0095 #define ARM_CPU_REV_SA1110_B0       4
0096 #define ARM_CPU_REV_SA1110_B1       5
0097 #define ARM_CPU_REV_SA1110_B2       6
0098 #define ARM_CPU_REV_SA1110_B4       8
0099
0100 #define ARM_CPU_XSCALE_ARCH_MASK    0xe000
0101 #define ARM_CPU_XSCALE_ARCH_V1      0x2000
0102 #define ARM_CPU_XSCALE_ARCH_V2      0x4000
0103 #define ARM_CPU_XSCALE_ARCH_V3      0x6000
0104
0105 /* Qualcomm implemented cores */
0106 #define ARM_CPU_PART_SCORPION       0x510002d0
0107
0108 #ifndef __ASSEMBLY__
0109
0110 #include <linux/stringify.h>
0111 #include <linux/kernel.h>
0112
0113 extern unsigned int processor_id;
0114 struct proc_info_list *lookup_processor(u32 midr);
0115
0116 #ifdef CONFIG_CPU_CP15
0117 #define read_cpuid(reg)                         \
0118     ({                              \
0119         unsigned int __val;                 \
0120         asm("mrc    p15, 0, %0, c0, c0, " __stringify(reg)  \
0121             : "=r" (__val)                  \
0122             :                           \
0123             : "cc");                        \
0124         __val;                          \
0125     })
0126
0127 /*
0128  * The memory clobber prevents gcc 4.5 from reordering the mrc before
0129  * any is_smp() tests, which can cause undefined instruction aborts on
0130  * ARM1136 r0 due to the missing extended CP15 registers.
0131  */
0132 #define read_cpuid_ext(ext_reg)                     \
0133     ({                              \
0134         unsigned int __val;                 \
0135         asm("mrc    p15, 0, %0, c0, " ext_reg       \
0136             : "=r" (__val)                  \
0137             :                           \
0138             : "memory");                    \
0139         __val;                          \
0140     })
0141
0142 #elif defined(CONFIG_CPU_V7M)
0143
0144 #include <asm/io.h>
0145 #include <asm/v7m.h>
0146
0147 #define read_cpuid(reg)                         \
0148     ({                              \
0149         WARN_ON_ONCE(1);                    \
0150         0;                          \
0151     })
0152
0153 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
0154 {
0155     return readl(BASEADDR_V7M_SCB + offset);
0156 }
0157
0158 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
0159
0160 /*
0161  * read_cpuid and read_cpuid_ext should only ever be called on machines that
0162  * have cp15 so warn on other usages.
0163  */
0164 #define read_cpuid(reg)                         \
0165     ({                              \
0166         WARN_ON_ONCE(1);                    \
0167         0;                          \
0168     })
0169
0170 #define read_cpuid_ext(reg) read_cpuid(reg)
0171
0172 #endif /* ifdef CONFIG_CPU_CP15 / else */
0173
0174 #ifdef CONFIG_CPU_CP15
0175 /*
0176  * The CPU ID never changes at run time, so we might as well tell the
0177  * compiler that it's constant.  Use this function to read the CPU ID
0178  * rather than directly reading processor_id or read_cpuid() directly.
0179  */
0180 static inline unsigned int __attribute_const__ read_cpuid_id(void)
0181 {
0182     return read_cpuid(CPUID_ID);
0183 }
0184
0185 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
0186 {
0187     return read_cpuid(CPUID_CACHETYPE);
0188 }
0189
0190 static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
0191 {
0192     return read_cpuid(CPUID_MPUIR);
0193 }
0194
0195 #elif defined(CONFIG_CPU_V7M)
0196
0197 static inline unsigned int __attribute_const__ read_cpuid_id(void)
0198 {
0199     return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
0200 }
0201
0202 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
0203 {
0204     return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
0205 }
0206
0207 static inline unsigned int __attribute_const__ read_cpuid_mputype(void)
0208 {
0209     return readl(BASEADDR_V7M_SCB + MPU_TYPE);
0210 }
0211
0212 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
0213
0214 static inline unsigned int __attribute_const__ read_cpuid_id(void)
0215 {
0216     return processor_id;
0217 }
0218
0219 #endif /* ifdef CONFIG_CPU_CP15 / else */
0220
0221 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
0222 {
0223     return (read_cpuid_id() & 0xFF000000) >> 24;
0224 }
0225
0226 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
0227 {
0228     return read_cpuid_id() & 0x0000000f;
0229 }
0230
0231 /*
0232  * The CPU part number is meaningless without referring to the CPU
0233  * implementer: implementers are free to define their own part numbers
0234  * which are permitted to clash with other implementer part numbers.
0235  */
0236 static inline unsigned int __attribute_const__ read_cpuid_part(void)
0237 {
0238     return read_cpuid_id() & ARM_CPU_PART_MASK;
0239 }
0240
0241 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
0242 {
0243     return read_cpuid_id() & 0xFFF0;
0244 }
0245
0246 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
0247 {
0248     return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
0249 }
0250
0251 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
0252 {
0253     return read_cpuid(CPUID_TCM);
0254 }
0255
0256 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
0257 {
0258     return read_cpuid(CPUID_MPIDR);
0259 }
0260
0261 /* StrongARM-11x0 CPUs */
0262 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
0263 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
0264
0265 /*
0266  * Intel's XScale3 core supports some v6 features (supersections, L2)
0267  * but advertises itself as v5 as it does not support the v6 ISA.  For
0268  * this reason, we need a way to explicitly test for this type of CPU.
0269  */
0270 #ifndef CONFIG_CPU_XSC3
0271 #define cpu_is_xsc3()   0
0272 #else
0273 static inline int cpu_is_xsc3(void)
0274 {
0275     unsigned int id;
0276     id = read_cpuid_id() & 0xffffe000;
0277     /* It covers both Intel ID and Marvell ID */
0278     if ((id == 0x69056000) || (id == 0x56056000))
0279         return 1;
0280
0281     return 0;
0282 }
0283 #endif
0284
0285 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
0286     !defined(CONFIG_CPU_MOHAWK)
0287 #define cpu_is_xscale_family() 0
0288 #else
0289 static inline int cpu_is_xscale_family(void)
0290 {
0291     unsigned int id;
0292     id = read_cpuid_id() & 0xffffe000;
0293
0294     switch (id) {
0295     case 0x69052000: /* Intel XScale 1 */
0296     case 0x69054000: /* Intel XScale 2 */
0297     case 0x69056000: /* Intel XScale 3 */
0298     case 0x56056000: /* Marvell XScale 3 */
0299     case 0x56158000: /* Marvell Mohawk */
0300         return 1;
0301     }
0302
0303     return 0;
0304 }
0305 #endif
0306
0307 /*
0308  * Marvell's PJ4 and PJ4B cores are based on V7 version,
0309  * but require a specical sequence for enabling coprocessors.
0310  * For this reason, we need a way to distinguish them.
0311  */
0312 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
0313 static inline int cpu_is_pj4(void)
0314 {
0315     unsigned int id;
0316
0317     id = read_cpuid_id();
0318     if ((id & 0xff0fff00) == 0x560f5800)
0319         return 1;
0320
0321     return 0;
0322 }
0323 #else
0324 #define cpu_is_pj4()    0
0325 #endif
0326
0327 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
0328                                   int field)
0329 {
0330     int feature = (features >> field) & 15;
0331
0332     /* feature registers are signed values */
0333     if (feature > 7)
0334         feature -= 16;
0335
0336     return feature;
0337 }
0338
0339 #define cpuid_feature_extract(reg, field) \
0340     cpuid_feature_extract_field(read_cpuid_ext(reg), field)
0341
0342 #endif /* __ASSEMBLY__ */
0343
0344 #endif