include/asm/cachetype.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_ARM_CACHETYPE_H
0003 #define __ASM_ARM_CACHETYPE_H
0004
0005 #define CACHEID_VIVT            (1 << 0)
0006 #define CACHEID_VIPT_NONALIASING    (1 << 1)
0007 #define CACHEID_VIPT_ALIASING       (1 << 2)
0008 #define CACHEID_VIPT            (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
0009 #define CACHEID_ASID_TAGGED     (1 << 3)
0010 #define CACHEID_VIPT_I_ALIASING     (1 << 4)
0011 #define CACHEID_PIPT            (1 << 5)
0012
0013 extern unsigned int cacheid;
0014
0015 #define cache_is_vivt()         cacheid_is(CACHEID_VIVT)
0016 #define cache_is_vipt()         cacheid_is(CACHEID_VIPT)
0017 #define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING)
0018 #define cache_is_vipt_aliasing()    cacheid_is(CACHEID_VIPT_ALIASING)
0019 #define icache_is_vivt_asid_tagged()    cacheid_is(CACHEID_ASID_TAGGED)
0020 #define icache_is_vipt_aliasing()   cacheid_is(CACHEID_VIPT_I_ALIASING)
0021 #define icache_is_pipt()        cacheid_is(CACHEID_PIPT)
0022
0023 /*
0024  * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
0025  * Mask out support which will never be present on newer CPUs.
0026  * - v6+ is never VIVT
0027  * - v7+ VIPT never aliases on D-side
0028  */
0029 #if __LINUX_ARM_ARCH__ >= 7
0030 #define __CACHEID_ARCH_MIN  (CACHEID_VIPT_NONALIASING |\
0031                  CACHEID_ASID_TAGGED |\
0032                  CACHEID_VIPT_I_ALIASING |\
0033                  CACHEID_PIPT)
0034 #elif __LINUX_ARM_ARCH__ >= 6
0035 #define __CACHEID_ARCH_MIN  (~CACHEID_VIVT)
0036 #else
0037 #define __CACHEID_ARCH_MIN  (~0)
0038 #endif
0039
0040 /*
0041  * Mask out support which isn't configured
0042  */
0043 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
0044 #define __CACHEID_ALWAYS    (CACHEID_VIVT)
0045 #define __CACHEID_NEVER     (~CACHEID_VIVT)
0046 #elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
0047 #define __CACHEID_ALWAYS    (0)
0048 #define __CACHEID_NEVER     (CACHEID_VIVT)
0049 #else
0050 #define __CACHEID_ALWAYS    (0)
0051 #define __CACHEID_NEVER     (0)
0052 #endif
0053
0054 static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
0055 {
0056     return (__CACHEID_ALWAYS & mask) |
0057            (~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
0058 }
0059
0060 #define CSSELR_ICACHE   1
0061 #define CSSELR_DCACHE   0
0062
0063 #define CSSELR_L1   (0 << 1)
0064 #define CSSELR_L2   (1 << 1)
0065 #define CSSELR_L3   (2 << 1)
0066 #define CSSELR_L4   (3 << 1)
0067 #define CSSELR_L5   (4 << 1)
0068 #define CSSELR_L6   (5 << 1)
0069 #define CSSELR_L7   (6 << 1)
0070
0071 #ifndef CONFIG_CPU_V7M
0072 static inline void set_csselr(unsigned int cache_selector)
0073 {
0074     asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
0075 }
0076
0077 static inline unsigned int read_ccsidr(void)
0078 {
0079     unsigned int val;
0080
0081     asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
0082     return val;
0083 }
0084 #else /* CONFIG_CPU_V7M */
0085 #include <linux/io.h>
0086 #include "asm/v7m.h"
0087
0088 static inline void set_csselr(unsigned int cache_selector)
0089 {
0090     writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
0091 }
0092
0093 static inline unsigned int read_ccsidr(void)
0094 {
0095     return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
0096 }
0097 #endif
0098
0099 #endif