include/asm/arch_timer.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASMARM_ARCH_TIMER_H
0003 #define __ASMARM_ARCH_TIMER_H
0004
0005 #include <asm/barrier.h>
0006 #include <asm/errno.h>
0007 #include <asm/hwcap.h>
0008 #include <linux/clocksource.h>
0009 #include <linux/init.h>
0010 #include <linux/io-64-nonatomic-lo-hi.h>
0011 #include <linux/types.h>
0012
0013 #include <clocksource/arm_arch_timer.h>
0014
0015 #ifdef CONFIG_ARM_ARCH_TIMER
0016 /* 32bit ARM doesn't know anything about timer errata... */
0017 #define has_erratum_handler(h)      (false)
0018 #define erratum_handler(h)      (arch_timer_##h)
0019
0020 int arch_timer_arch_init(void);
0021
0022 /*
0023  * These register accessors are marked inline so the compiler can
0024  * nicely work out which register we want, and chuck away the rest of
0025  * the code. At least it does so with a recent GCC (4.6.3).
0026  */
0027 static __always_inline
0028 void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
0029 {
0030     if (access == ARCH_TIMER_PHYS_ACCESS) {
0031         switch (reg) {
0032         case ARCH_TIMER_REG_CTRL:
0033             asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val));
0034             isb();
0035             break;
0036         case ARCH_TIMER_REG_CVAL:
0037             asm volatile("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
0038             break;
0039         default:
0040             BUILD_BUG();
0041         }
0042     } else if (access == ARCH_TIMER_VIRT_ACCESS) {
0043         switch (reg) {
0044         case ARCH_TIMER_REG_CTRL:
0045             asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val));
0046             isb();
0047             break;
0048         case ARCH_TIMER_REG_CVAL:
0049             asm volatile("mcrr p15, 3, %Q0, %R0, c14" : : "r" (val));
0050             break;
0051         default:
0052             BUILD_BUG();
0053         }
0054     } else {
0055         BUILD_BUG();
0056     }
0057 }
0058
0059 static __always_inline
0060 u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
0061 {
0062     u32 val = 0;
0063
0064     if (access == ARCH_TIMER_PHYS_ACCESS) {
0065         switch (reg) {
0066         case ARCH_TIMER_REG_CTRL:
0067             asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
0068             break;
0069         default:
0070             BUILD_BUG();
0071         }
0072     } else if (access == ARCH_TIMER_VIRT_ACCESS) {
0073         switch (reg) {
0074         case ARCH_TIMER_REG_CTRL:
0075             asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
0076             break;
0077         default:
0078             BUILD_BUG();
0079         }
0080     } else {
0081         BUILD_BUG();
0082     }
0083
0084     return val;
0085 }
0086
0087 static inline u32 arch_timer_get_cntfrq(void)
0088 {
0089     u32 val;
0090     asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
0091     return val;
0092 }
0093
0094 static inline u64 __arch_counter_get_cntpct(void)
0095 {
0096     u64 cval;
0097
0098     isb();
0099     asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
0100     return cval;
0101 }
0102
0103 static inline u64 __arch_counter_get_cntpct_stable(void)
0104 {
0105     return __arch_counter_get_cntpct();
0106 }
0107
0108 static inline u64 __arch_counter_get_cntvct(void)
0109 {
0110     u64 cval;
0111
0112     isb();
0113     asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
0114     return cval;
0115 }
0116
0117 static inline u64 __arch_counter_get_cntvct_stable(void)
0118 {
0119     return __arch_counter_get_cntvct();
0120 }
0121
0122 static inline u32 arch_timer_get_cntkctl(void)
0123 {
0124     u32 cntkctl;
0125     asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
0126     return cntkctl;
0127 }
0128
0129 static inline void arch_timer_set_cntkctl(u32 cntkctl)
0130 {
0131     asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
0132     isb();
0133 }
0134
0135 static inline void arch_timer_set_evtstrm_feature(void)
0136 {
0137     elf_hwcap |= HWCAP_EVTSTRM;
0138 }
0139
0140 static inline bool arch_timer_have_evtstrm_feature(void)
0141 {
0142     return elf_hwcap & HWCAP_EVTSTRM;
0143 }
0144 #endif
0145
0146 #endif