include/asm/arch_gicv3.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/include/asm/arch_gicv3.h
0004  *
0005  * Copyright (C) 2015 ARM Ltd.
0006  */
0007 #ifndef __ASM_ARCH_GICV3_H
0008 #define __ASM_ARCH_GICV3_H
0009
0010 #ifndef __ASSEMBLY__
0011
0012 #include <linux/io.h>
0013 #include <linux/io-64-nonatomic-lo-hi.h>
0014 #include <asm/barrier.h>
0015 #include <asm/cacheflush.h>
0016 #include <asm/cp15.h>
0017
0018 #define ICC_EOIR1           __ACCESS_CP15(c12, 0, c12, 1)
0019 #define ICC_DIR             __ACCESS_CP15(c12, 0, c11, 1)
0020 #define ICC_IAR1            __ACCESS_CP15(c12, 0, c12, 0)
0021 #define ICC_SGI1R           __ACCESS_CP15_64(0, c12)
0022 #define ICC_PMR             __ACCESS_CP15(c4, 0, c6, 0)
0023 #define ICC_CTLR            __ACCESS_CP15(c12, 0, c12, 4)
0024 #define ICC_SRE             __ACCESS_CP15(c12, 0, c12, 5)
0025 #define ICC_IGRPEN1         __ACCESS_CP15(c12, 0, c12, 7)
0026 #define ICC_BPR1            __ACCESS_CP15(c12, 0, c12, 3)
0027 #define ICC_RPR             __ACCESS_CP15(c12, 0, c11, 3)
0028
0029 #define __ICC_AP0Rx(x)          __ACCESS_CP15(c12, 0, c8, 4 | x)
0030 #define ICC_AP0R0           __ICC_AP0Rx(0)
0031 #define ICC_AP0R1           __ICC_AP0Rx(1)
0032 #define ICC_AP0R2           __ICC_AP0Rx(2)
0033 #define ICC_AP0R3           __ICC_AP0Rx(3)
0034
0035 #define __ICC_AP1Rx(x)          __ACCESS_CP15(c12, 0, c9, x)
0036 #define ICC_AP1R0           __ICC_AP1Rx(0)
0037 #define ICC_AP1R1           __ICC_AP1Rx(1)
0038 #define ICC_AP1R2           __ICC_AP1Rx(2)
0039 #define ICC_AP1R3           __ICC_AP1Rx(3)
0040
0041 #define CPUIF_MAP(a32, a64)         \
0042 static inline void write_ ## a64(u32 val)   \
0043 {                       \
0044     write_sysreg(val, a32);         \
0045 }                       \
0046 static inline u32 read_ ## a64(void)        \
0047 {                       \
0048     return read_sysreg(a32);        \
0049 }                       \
0050
0051 CPUIF_MAP(ICC_EOIR1, ICC_EOIR1_EL1)
0052 CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
0053 CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
0054 CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
0055 CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
0056 CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
0057 CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
0058 CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
0059 CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
0060 CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
0061
0062 #define read_gicreg(r)                 read_##r()
0063 #define write_gicreg(v, r)             write_##r(v)
0064
0065 /* Low-level accessors */
0066
0067 static inline void gic_write_dir(u32 val)
0068 {
0069     write_sysreg(val, ICC_DIR);
0070     isb();
0071 }
0072
0073 static inline u32 gic_read_iar(void)
0074 {
0075     u32 irqstat = read_sysreg(ICC_IAR1);
0076
0077     dsb(sy);
0078
0079     return irqstat;
0080 }
0081
0082 static inline void gic_write_ctlr(u32 val)
0083 {
0084     write_sysreg(val, ICC_CTLR);
0085     isb();
0086 }
0087
0088 static inline u32 gic_read_ctlr(void)
0089 {
0090     return read_sysreg(ICC_CTLR);
0091 }
0092
0093 static inline void gic_write_grpen1(u32 val)
0094 {
0095     write_sysreg(val, ICC_IGRPEN1);
0096     isb();
0097 }
0098
0099 static inline void gic_write_sgi1r(u64 val)
0100 {
0101     write_sysreg(val, ICC_SGI1R);
0102 }
0103
0104 static inline u32 gic_read_sre(void)
0105 {
0106     return read_sysreg(ICC_SRE);
0107 }
0108
0109 static inline void gic_write_sre(u32 val)
0110 {
0111     write_sysreg(val, ICC_SRE);
0112     isb();
0113 }
0114
0115 static inline void gic_write_bpr1(u32 val)
0116 {
0117     write_sysreg(val, ICC_BPR1);
0118 }
0119
0120 static inline u32 gic_read_pmr(void)
0121 {
0122     return read_sysreg(ICC_PMR);
0123 }
0124
0125 static inline void gic_write_pmr(u32 val)
0126 {
0127     write_sysreg(val, ICC_PMR);
0128 }
0129
0130 static inline u32 gic_read_rpr(void)
0131 {
0132     return read_sysreg(ICC_RPR);
0133 }
0134
0135 /*
0136  * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
0137  * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
0138  * make much sense.
0139  * Moreover, 64bit I/O emulation is extremely difficult to implement on
0140  * AArch32, since the syndrome register doesn't provide any information for
0141  * them.
0142  * Consequently, the following IO helpers use 32bit accesses.
0143  */
0144 static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
0145 {
0146     writel_relaxed((u32)val, addr);
0147     writel_relaxed((u32)(val >> 32), addr + 4);
0148 }
0149
0150 static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
0151 {
0152     u64 val;
0153
0154     val = readl_relaxed(addr);
0155     val |= (u64)readl_relaxed(addr + 4) << 32;
0156     return val;
0157 }
0158
0159 #define gic_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
0160
0161 /*
0162  *  GICD_IROUTERn, contain the affinity values associated to each interrupt.
0163  *  The upper-word (aff3) will always be 0, so there is no need for a lock.
0164  */
0165 #define gic_write_irouter(v, c)     __gic_writeq_nonatomic(v, c)
0166
0167 /*
0168  * GICR_TYPER is an ID register and doesn't need atomicity.
0169  */
0170 #define gic_read_typer(c)       __gic_readq_nonatomic(c)
0171
0172 /*
0173  * GITS_BASER - hi and lo bits may be accessed independently.
0174  */
0175 #define gits_read_baser(c)      __gic_readq_nonatomic(c)
0176 #define gits_write_baser(v, c)      __gic_writeq_nonatomic(v, c)
0177
0178 /*
0179  * GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
0180  * won't be being used during any updates and can be changed non-atomically
0181  */
0182 #define gicr_read_propbaser(c)      __gic_readq_nonatomic(c)
0183 #define gicr_write_propbaser(v, c)  __gic_writeq_nonatomic(v, c)
0184 #define gicr_read_pendbaser(c)      __gic_readq_nonatomic(c)
0185 #define gicr_write_pendbaser(v, c)  __gic_writeq_nonatomic(v, c)
0186
0187 /*
0188  * GICR_xLPIR - only the lower bits are significant
0189  */
0190 #define gic_read_lpir(c)        readl_relaxed(c)
0191 #define gic_write_lpir(v, c)        writel_relaxed(lower_32_bits(v), c)
0192
0193 /*
0194  * GITS_TYPER is an ID register and doesn't need atomicity.
0195  */
0196 #define gits_read_typer(c)      __gic_readq_nonatomic(c)
0197
0198 /*
0199  * GITS_CBASER - hi and lo bits may be accessed independently.
0200  */
0201 #define gits_read_cbaser(c)     __gic_readq_nonatomic(c)
0202 #define gits_write_cbaser(v, c)     __gic_writeq_nonatomic(v, c)
0203
0204 /*
0205  * GITS_CWRITER - hi and lo bits may be accessed independently.
0206  */
0207 #define gits_write_cwriter(v, c)    __gic_writeq_nonatomic(v, c)
0208
0209 /*
0210  * GICR_VPROPBASER - hi and lo bits may be accessed independently.
0211  */
0212 #define gicr_read_vpropbaser(c)     __gic_readq_nonatomic(c)
0213 #define gicr_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)
0214
0215 /*
0216  * GICR_VPENDBASER - the Valid bit must be cleared before changing
0217  * anything else.
0218  */
0219 static inline void gicr_write_vpendbaser(u64 val, void __iomem *addr)
0220 {
0221     u32 tmp;
0222
0223     tmp = readl_relaxed(addr + 4);
0224     if (tmp & (GICR_VPENDBASER_Valid >> 32)) {
0225         tmp &= ~(GICR_VPENDBASER_Valid >> 32);
0226         writel_relaxed(tmp, addr + 4);
0227     }
0228
0229     /*
0230      * Use the fact that __gic_writeq_nonatomic writes the second
0231      * half of the 64bit quantity after the first.
0232      */
0233     __gic_writeq_nonatomic(val, addr);
0234 }
0235
0236 #define gicr_read_vpendbaser(c)     __gic_readq_nonatomic(c)
0237
0238 static inline bool gic_prio_masking_enabled(void)
0239 {
0240     return false;
0241 }
0242
0243 static inline void gic_pmr_mask_irqs(void)
0244 {
0245     /* Should not get called. */
0246     WARN_ON_ONCE(true);
0247 }
0248
0249 static inline void gic_arch_enable_irqs(void)
0250 {
0251     /* Should not get called. */
0252     WARN_ON_ONCE(true);
0253 }
0254
0255 #endif /* !__ASSEMBLY__ */
0256 #endif /* !__ASM_ARCH_GICV3_H */