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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/arch/arm/common/sa1111.c
0004  *
0005  * SA1111 support
0006  *
0007  * Original code by John Dorsey
0008  *
0009  * This file contains all generic SA1111 support.
0010  *
0011  * All initialization functions provided here are intended to be called
0012  * from machine specific code with proper arguments when required.
0013  */
0014 #include <linux/module.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/init.h>
0017 #include <linux/irq.h>
0018 #include <linux/kernel.h>
0019 #include <linux/delay.h>
0020 #include <linux/errno.h>
0021 #include <linux/ioport.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/slab.h>
0024 #include <linux/spinlock.h>
0025 #include <linux/dma-map-ops.h>
0026 #include <linux/clk.h>
0027 #include <linux/io.h>
0028 
0029 #include <asm/mach/irq.h>
0030 #include <asm/mach-types.h>
0031 #include <linux/sizes.h>
0032 
0033 #include <asm/hardware/sa1111.h>
0034 
0035 #ifdef CONFIG_ARCH_SA1100
0036 #include <mach/hardware.h>
0037 #endif
0038 
0039 /* SA1111 IRQs */
0040 #define IRQ_GPAIN0      (0)
0041 #define IRQ_GPAIN1      (1)
0042 #define IRQ_GPAIN2      (2)
0043 #define IRQ_GPAIN3      (3)
0044 #define IRQ_GPBIN0      (4)
0045 #define IRQ_GPBIN1      (5)
0046 #define IRQ_GPBIN2      (6)
0047 #define IRQ_GPBIN3      (7)
0048 #define IRQ_GPBIN4      (8)
0049 #define IRQ_GPBIN5      (9)
0050 #define IRQ_GPCIN0      (10)
0051 #define IRQ_GPCIN1      (11)
0052 #define IRQ_GPCIN2      (12)
0053 #define IRQ_GPCIN3      (13)
0054 #define IRQ_GPCIN4      (14)
0055 #define IRQ_GPCIN5      (15)
0056 #define IRQ_GPCIN6      (16)
0057 #define IRQ_GPCIN7      (17)
0058 #define IRQ_MSTXINT     (18)
0059 #define IRQ_MSRXINT     (19)
0060 #define IRQ_MSSTOPERRINT    (20)
0061 #define IRQ_TPTXINT     (21)
0062 #define IRQ_TPRXINT     (22)
0063 #define IRQ_TPSTOPERRINT    (23)
0064 #define SSPXMTINT       (24)
0065 #define SSPRCVINT       (25)
0066 #define SSPROR          (26)
0067 #define AUDXMTDMADONEA      (32)
0068 #define AUDRCVDMADONEA      (33)
0069 #define AUDXMTDMADONEB      (34)
0070 #define AUDRCVDMADONEB      (35)
0071 #define AUDTFSR         (36)
0072 #define AUDRFSR         (37)
0073 #define AUDTUR          (38)
0074 #define AUDROR          (39)
0075 #define AUDDTS          (40)
0076 #define AUDRDD          (41)
0077 #define AUDSTO          (42)
0078 #define IRQ_USBPWR      (43)
0079 #define IRQ_HCIM        (44)
0080 #define IRQ_HCIBUFFACC      (45)
0081 #define IRQ_HCIRMTWKP       (46)
0082 #define IRQ_NHCIMFCIR       (47)
0083 #define IRQ_USB_PORT_RESUME (48)
0084 #define IRQ_S0_READY_NINT   (49)
0085 #define IRQ_S1_READY_NINT   (50)
0086 #define IRQ_S0_CD_VALID     (51)
0087 #define IRQ_S1_CD_VALID     (52)
0088 #define IRQ_S0_BVD1_STSCHG  (53)
0089 #define IRQ_S1_BVD1_STSCHG  (54)
0090 #define SA1111_IRQ_NR       (55)
0091 
0092 extern void sa1110_mb_enable(void);
0093 extern void sa1110_mb_disable(void);
0094 
0095 /*
0096  * We keep the following data for the overall SA1111.  Note that the
0097  * struct device and struct resource are "fake"; they should be supplied
0098  * by the bus above us.  However, in the interests of getting all SA1111
0099  * drivers converted over to the device model, we provide this as an
0100  * anchor point for all the other drivers.
0101  */
0102 struct sa1111 {
0103     struct device   *dev;
0104     struct clk  *clk;
0105     unsigned long   phys;
0106     int     irq;
0107     int     irq_base;   /* base for cascaded on-chip IRQs */
0108     spinlock_t  lock;
0109     void __iomem    *base;
0110     struct sa1111_platform_data *pdata;
0111     struct irq_domain *irqdomain;
0112     struct gpio_chip gc;
0113 #ifdef CONFIG_PM
0114     void        *saved_state;
0115 #endif
0116 };
0117 
0118 /*
0119  * We _really_ need to eliminate this.  Its only users
0120  * are the PWM and DMA checking code.
0121  */
0122 static struct sa1111 *g_sa1111;
0123 
0124 struct sa1111_dev_info {
0125     unsigned long   offset;
0126     unsigned long   skpcr_mask;
0127     bool        dma;
0128     unsigned int    devid;
0129     unsigned int    hwirq[6];
0130 };
0131 
0132 static struct sa1111_dev_info sa1111_devices[] = {
0133     {
0134         .offset     = SA1111_USB,
0135         .skpcr_mask = SKPCR_UCLKEN,
0136         .dma        = true,
0137         .devid      = SA1111_DEVID_USB,
0138         .hwirq = {
0139             IRQ_USBPWR,
0140             IRQ_HCIM,
0141             IRQ_HCIBUFFACC,
0142             IRQ_HCIRMTWKP,
0143             IRQ_NHCIMFCIR,
0144             IRQ_USB_PORT_RESUME
0145         },
0146     },
0147     {
0148         .offset     = 0x0600,
0149         .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
0150         .dma        = true,
0151         .devid      = SA1111_DEVID_SAC,
0152         .hwirq = {
0153             AUDXMTDMADONEA,
0154             AUDXMTDMADONEB,
0155             AUDRCVDMADONEA,
0156             AUDRCVDMADONEB
0157         },
0158     },
0159     {
0160         .offset     = 0x0800,
0161         .skpcr_mask = SKPCR_SCLKEN,
0162         .devid      = SA1111_DEVID_SSP,
0163     },
0164     {
0165         .offset     = SA1111_KBD,
0166         .skpcr_mask = SKPCR_PTCLKEN,
0167         .devid      = SA1111_DEVID_PS2_KBD,
0168         .hwirq = {
0169             IRQ_TPRXINT,
0170             IRQ_TPTXINT
0171         },
0172     },
0173     {
0174         .offset     = SA1111_MSE,
0175         .skpcr_mask = SKPCR_PMCLKEN,
0176         .devid      = SA1111_DEVID_PS2_MSE,
0177         .hwirq = {
0178             IRQ_MSRXINT,
0179             IRQ_MSTXINT
0180         },
0181     },
0182     {
0183         .offset     = 0x1800,
0184         .skpcr_mask = 0,
0185         .devid      = SA1111_DEVID_PCMCIA,
0186         .hwirq = {
0187             IRQ_S0_READY_NINT,
0188             IRQ_S0_CD_VALID,
0189             IRQ_S0_BVD1_STSCHG,
0190             IRQ_S1_READY_NINT,
0191             IRQ_S1_CD_VALID,
0192             IRQ_S1_BVD1_STSCHG,
0193         },
0194     },
0195 };
0196 
0197 static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq)
0198 {
0199     return irq_create_mapping(sachip->irqdomain, hwirq);
0200 }
0201 
0202 /*
0203  * SA1111 interrupt support.  Since clearing an IRQ while there are
0204  * active IRQs causes the interrupt output to pulse, the upper levels
0205  * will call us again if there are more interrupts to process.
0206  */
0207 static void sa1111_irq_handler(struct irq_desc *desc)
0208 {
0209     unsigned int stat0, stat1, i;
0210     struct sa1111 *sachip = irq_desc_get_handler_data(desc);
0211     struct irq_domain *irqdomain;
0212     void __iomem *mapbase = sachip->base + SA1111_INTC;
0213 
0214     stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0);
0215     stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1);
0216 
0217     writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0);
0218 
0219     desc->irq_data.chip->irq_ack(&desc->irq_data);
0220 
0221     writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
0222 
0223     if (stat0 == 0 && stat1 == 0) {
0224         do_bad_IRQ(desc);
0225         return;
0226     }
0227 
0228     irqdomain = sachip->irqdomain;
0229 
0230     for (i = 0; stat0; i++, stat0 >>= 1)
0231         if (stat0 & 1)
0232             generic_handle_domain_irq(irqdomain, i);
0233 
0234     for (i = 32; stat1; i++, stat1 >>= 1)
0235         if (stat1 & 1)
0236             generic_handle_domain_irq(irqdomain, i);
0237 
0238     /* For level-based interrupts */
0239     desc->irq_data.chip->irq_unmask(&desc->irq_data);
0240 }
0241 
0242 static u32 sa1111_irqmask(struct irq_data *d)
0243 {
0244     return BIT(irqd_to_hwirq(d) & 31);
0245 }
0246 
0247 static int sa1111_irqbank(struct irq_data *d)
0248 {
0249     return (irqd_to_hwirq(d) / 32) * 4;
0250 }
0251 
0252 static void sa1111_ack_irq(struct irq_data *d)
0253 {
0254 }
0255 
0256 static void sa1111_mask_irq(struct irq_data *d)
0257 {
0258     struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
0259     void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
0260     u32 ie;
0261 
0262     ie = readl_relaxed(mapbase + SA1111_INTEN0);
0263     ie &= ~sa1111_irqmask(d);
0264     writel(ie, mapbase + SA1111_INTEN0);
0265 }
0266 
0267 static void sa1111_unmask_irq(struct irq_data *d)
0268 {
0269     struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
0270     void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
0271     u32 ie;
0272 
0273     ie = readl_relaxed(mapbase + SA1111_INTEN0);
0274     ie |= sa1111_irqmask(d);
0275     writel_relaxed(ie, mapbase + SA1111_INTEN0);
0276 }
0277 
0278 /*
0279  * Attempt to re-trigger the interrupt.  The SA1111 contains a register
0280  * (INTSET) which claims to do this.  However, in practice no amount of
0281  * manipulation of INTEN and INTSET guarantees that the interrupt will
0282  * be triggered.  In fact, its very difficult, if not impossible to get
0283  * INTSET to re-trigger the interrupt.
0284  */
0285 static int sa1111_retrigger_irq(struct irq_data *d)
0286 {
0287     struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
0288     void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
0289     u32 ip, mask = sa1111_irqmask(d);
0290     int i;
0291 
0292     ip = readl_relaxed(mapbase + SA1111_INTPOL0);
0293     for (i = 0; i < 8; i++) {
0294         writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0);
0295         writel_relaxed(ip, mapbase + SA1111_INTPOL0);
0296         if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask)
0297             break;
0298     }
0299 
0300     if (i == 8) {
0301         pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
0302                d->irq);
0303         return 0;
0304     }
0305 
0306     return 1;
0307 }
0308 
0309 static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
0310 {
0311     struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
0312     void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
0313     u32 ip, mask = sa1111_irqmask(d);
0314 
0315     if (flags == IRQ_TYPE_PROBE)
0316         return 0;
0317 
0318     if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
0319         return -EINVAL;
0320 
0321     ip = readl_relaxed(mapbase + SA1111_INTPOL0);
0322     if (flags & IRQ_TYPE_EDGE_RISING)
0323         ip &= ~mask;
0324     else
0325         ip |= mask;
0326     writel_relaxed(ip, mapbase + SA1111_INTPOL0);
0327     writel_relaxed(ip, mapbase + SA1111_WAKEPOL0);
0328 
0329     return 0;
0330 }
0331 
0332 static int sa1111_wake_irq(struct irq_data *d, unsigned int on)
0333 {
0334     struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
0335     void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
0336     u32 we, mask = sa1111_irqmask(d);
0337 
0338     we = readl_relaxed(mapbase + SA1111_WAKEEN0);
0339     if (on)
0340         we |= mask;
0341     else
0342         we &= ~mask;
0343     writel_relaxed(we, mapbase + SA1111_WAKEEN0);
0344 
0345     return 0;
0346 }
0347 
0348 static struct irq_chip sa1111_irq_chip = {
0349     .name       = "SA1111",
0350     .irq_ack    = sa1111_ack_irq,
0351     .irq_mask   = sa1111_mask_irq,
0352     .irq_unmask = sa1111_unmask_irq,
0353     .irq_retrigger  = sa1111_retrigger_irq,
0354     .irq_set_type   = sa1111_type_irq,
0355     .irq_set_wake   = sa1111_wake_irq,
0356 };
0357 
0358 static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq,
0359     irq_hw_number_t hwirq)
0360 {
0361     struct sa1111 *sachip = d->host_data;
0362 
0363     /* Disallow unavailable interrupts */
0364     if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA)
0365         return -EINVAL;
0366 
0367     irq_set_chip_data(irq, sachip);
0368     irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
0369     irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
0370 
0371     return 0;
0372 }
0373 
0374 static const struct irq_domain_ops sa1111_irqdomain_ops = {
0375     .map = sa1111_irqdomain_map,
0376     .xlate = irq_domain_xlate_twocell,
0377 };
0378 
0379 static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
0380 {
0381     void __iomem *irqbase = sachip->base + SA1111_INTC;
0382     int ret;
0383 
0384     /*
0385      * We're guaranteed that this region hasn't been taken.
0386      */
0387     request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
0388 
0389     ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
0390     if (ret <= 0) {
0391         dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
0392             SA1111_IRQ_NR, ret);
0393         if (ret == 0)
0394             ret = -EINVAL;
0395         return ret;
0396     }
0397 
0398     sachip->irq_base = ret;
0399 
0400     /* disable all IRQs */
0401     writel_relaxed(0, irqbase + SA1111_INTEN0);
0402     writel_relaxed(0, irqbase + SA1111_INTEN1);
0403     writel_relaxed(0, irqbase + SA1111_WAKEEN0);
0404     writel_relaxed(0, irqbase + SA1111_WAKEEN1);
0405 
0406     /*
0407      * detect on rising edge.  Note: Feb 2001 Errata for SA1111
0408      * specifies that S0ReadyInt and S1ReadyInt should be '1'.
0409      */
0410     writel_relaxed(0, irqbase + SA1111_INTPOL0);
0411     writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) |
0412                BIT(IRQ_S1_READY_NINT & 31),
0413                irqbase + SA1111_INTPOL1);
0414 
0415     /* clear all IRQs */
0416     writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0);
0417     writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1);
0418 
0419     sachip->irqdomain = irq_domain_add_linear(NULL, SA1111_IRQ_NR,
0420                           &sa1111_irqdomain_ops,
0421                           sachip);
0422     if (!sachip->irqdomain) {
0423         irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
0424         return -ENOMEM;
0425     }
0426 
0427     irq_domain_associate_many(sachip->irqdomain,
0428                   sachip->irq_base + IRQ_GPAIN0,
0429                   IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0);
0430     irq_domain_associate_many(sachip->irqdomain,
0431                   sachip->irq_base + AUDXMTDMADONEA,
0432                   AUDXMTDMADONEA,
0433                   IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA);
0434 
0435     /*
0436      * Register SA1111 interrupt
0437      */
0438     irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
0439     irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
0440                      sachip);
0441 
0442     dev_info(sachip->dev, "Providing IRQ%u-%u\n",
0443         sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
0444 
0445     return 0;
0446 }
0447 
0448 static void sa1111_remove_irq(struct sa1111 *sachip)
0449 {
0450     struct irq_domain *domain = sachip->irqdomain;
0451     void __iomem *irqbase = sachip->base + SA1111_INTC;
0452     int i;
0453 
0454     /* disable all IRQs */
0455     writel_relaxed(0, irqbase + SA1111_INTEN0);
0456     writel_relaxed(0, irqbase + SA1111_INTEN1);
0457     writel_relaxed(0, irqbase + SA1111_WAKEEN0);
0458     writel_relaxed(0, irqbase + SA1111_WAKEEN1);
0459 
0460     irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
0461     for (i = 0; i < SA1111_IRQ_NR; i++)
0462         irq_dispose_mapping(irq_find_mapping(domain, i));
0463     irq_domain_remove(domain);
0464 
0465     release_mem_region(sachip->phys + SA1111_INTC, 512);
0466 }
0467 
0468 enum {
0469     SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR),
0470     SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR),
0471     SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR),
0472     SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR),
0473     SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR),
0474 };
0475 
0476 static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc)
0477 {
0478     return container_of(gc, struct sa1111, gc);
0479 }
0480 
0481 static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset)
0482 {
0483     void __iomem *reg = sachip->base + SA1111_GPIO;
0484 
0485     if (offset < 4)
0486         return reg + SA1111_GPIO_PADDR;
0487     if (offset < 10)
0488         return reg + SA1111_GPIO_PBDDR;
0489     if (offset < 18)
0490         return reg + SA1111_GPIO_PCDDR;
0491     return NULL;
0492 }
0493 
0494 static u32 sa1111_gpio_map_bit(unsigned offset)
0495 {
0496     if (offset < 4)
0497         return BIT(offset);
0498     if (offset < 10)
0499         return BIT(offset - 4);
0500     if (offset < 18)
0501         return BIT(offset - 10);
0502     return 0;
0503 }
0504 
0505 static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set)
0506 {
0507     u32 val;
0508 
0509     val = readl_relaxed(reg);
0510     val &= ~mask;
0511     val |= mask & set;
0512     writel_relaxed(val, reg);
0513 }
0514 
0515 static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
0516 {
0517     struct sa1111 *sachip = gc_to_sa1111(gc);
0518     void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
0519     u32 mask = sa1111_gpio_map_bit(offset);
0520 
0521     return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask);
0522 }
0523 
0524 static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
0525 {
0526     struct sa1111 *sachip = gc_to_sa1111(gc);
0527     unsigned long flags;
0528     void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
0529     u32 mask = sa1111_gpio_map_bit(offset);
0530 
0531     spin_lock_irqsave(&sachip->lock, flags);
0532     sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask);
0533     sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask);
0534     spin_unlock_irqrestore(&sachip->lock, flags);
0535 
0536     return 0;
0537 }
0538 
0539 static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
0540     int value)
0541 {
0542     struct sa1111 *sachip = gc_to_sa1111(gc);
0543     unsigned long flags;
0544     void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
0545     u32 mask = sa1111_gpio_map_bit(offset);
0546 
0547     spin_lock_irqsave(&sachip->lock, flags);
0548     sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
0549     sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
0550     sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0);
0551     sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0);
0552     spin_unlock_irqrestore(&sachip->lock, flags);
0553 
0554     return 0;
0555 }
0556 
0557 static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset)
0558 {
0559     struct sa1111 *sachip = gc_to_sa1111(gc);
0560     void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
0561     u32 mask = sa1111_gpio_map_bit(offset);
0562 
0563     return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask);
0564 }
0565 
0566 static void sa1111_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
0567 {
0568     struct sa1111 *sachip = gc_to_sa1111(gc);
0569     unsigned long flags;
0570     void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
0571     u32 mask = sa1111_gpio_map_bit(offset);
0572 
0573     spin_lock_irqsave(&sachip->lock, flags);
0574     sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
0575     sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
0576     spin_unlock_irqrestore(&sachip->lock, flags);
0577 }
0578 
0579 static void sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
0580     unsigned long *bits)
0581 {
0582     struct sa1111 *sachip = gc_to_sa1111(gc);
0583     unsigned long flags;
0584     void __iomem *reg = sachip->base + SA1111_GPIO;
0585     u32 msk, val;
0586 
0587     msk = *mask;
0588     val = *bits;
0589 
0590     spin_lock_irqsave(&sachip->lock, flags);
0591     sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val);
0592     sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val);
0593     sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4);
0594     sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4);
0595     sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12);
0596     sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12);
0597     spin_unlock_irqrestore(&sachip->lock, flags);
0598 }
0599 
0600 static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
0601 {
0602     struct sa1111 *sachip = gc_to_sa1111(gc);
0603 
0604     return sa1111_map_irq(sachip, offset);
0605 }
0606 
0607 static int sa1111_setup_gpios(struct sa1111 *sachip)
0608 {
0609     sachip->gc.label = "sa1111";
0610     sachip->gc.parent = sachip->dev;
0611     sachip->gc.owner = THIS_MODULE;
0612     sachip->gc.get_direction = sa1111_gpio_get_direction;
0613     sachip->gc.direction_input = sa1111_gpio_direction_input;
0614     sachip->gc.direction_output = sa1111_gpio_direction_output;
0615     sachip->gc.get = sa1111_gpio_get;
0616     sachip->gc.set = sa1111_gpio_set;
0617     sachip->gc.set_multiple = sa1111_gpio_set_multiple;
0618     sachip->gc.to_irq = sa1111_gpio_to_irq;
0619     sachip->gc.base = -1;
0620     sachip->gc.ngpio = 18;
0621 
0622     return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
0623 }
0624 
0625 /*
0626  * Bring the SA1111 out of reset.  This requires a set procedure:
0627  *  1. nRESET asserted (by hardware)
0628  *  2. CLK turned on from SA1110
0629  *  3. nRESET deasserted
0630  *  4. VCO turned on, PLL_BYPASS turned off
0631  *  5. Wait lock time, then assert RCLKEn
0632  *  7. PCR set to allow clocking of individual functions
0633  *
0634  * Until we've done this, the only registers we can access are:
0635  *   SBI_SKCR
0636  *   SBI_SMCR
0637  *   SBI_SKID
0638  */
0639 static void sa1111_wake(struct sa1111 *sachip)
0640 {
0641     unsigned long flags, r;
0642 
0643     spin_lock_irqsave(&sachip->lock, flags);
0644 
0645     clk_enable(sachip->clk);
0646 
0647     /*
0648      * Turn VCO on, and disable PLL Bypass.
0649      */
0650     r = readl_relaxed(sachip->base + SA1111_SKCR);
0651     r &= ~SKCR_VCO_OFF;
0652     writel_relaxed(r, sachip->base + SA1111_SKCR);
0653     r |= SKCR_PLL_BYPASS | SKCR_OE_EN;
0654     writel_relaxed(r, sachip->base + SA1111_SKCR);
0655 
0656     /*
0657      * Wait lock time.  SA1111 manual _doesn't_
0658      * specify a figure for this!  We choose 100us.
0659      */
0660     udelay(100);
0661 
0662     /*
0663      * Enable RCLK.  We also ensure that RDYEN is set.
0664      */
0665     r |= SKCR_RCLKEN | SKCR_RDYEN;
0666     writel_relaxed(r, sachip->base + SA1111_SKCR);
0667 
0668     /*
0669      * Wait 14 RCLK cycles for the chip to finish coming out
0670      * of reset. (RCLK=24MHz).  This is 590ns.
0671      */
0672     udelay(1);
0673 
0674     /*
0675      * Ensure all clocks are initially off.
0676      */
0677     writel_relaxed(0, sachip->base + SA1111_SKPCR);
0678 
0679     spin_unlock_irqrestore(&sachip->lock, flags);
0680 }
0681 
0682 #ifdef CONFIG_ARCH_SA1100
0683 
0684 static u32 sa1111_dma_mask[] = {
0685     ~0,
0686     ~(1 << 20),
0687     ~(1 << 23),
0688     ~(1 << 24),
0689     ~(1 << 25),
0690     ~(1 << 20),
0691     ~(1 << 20),
0692     0,
0693 };
0694 
0695 /*
0696  * Configure the SA1111 shared memory controller.
0697  */
0698 void
0699 sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
0700              unsigned int cas_latency)
0701 {
0702     unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC);
0703 
0704     if (cas_latency == 3)
0705         smcr |= SMCR_CLAT;
0706 
0707     writel_relaxed(smcr, sachip->base + SA1111_SMCR);
0708 
0709     /*
0710      * Now clear the bits in the DMA mask to work around the SA1111
0711      * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion
0712      * Chip Specification Update, June 2000, Erratum #7).
0713      */
0714     if (sachip->dev->dma_mask)
0715         *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
0716 
0717     sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
0718 }
0719 #endif
0720 
0721 static void sa1111_dev_release(struct device *_dev)
0722 {
0723     struct sa1111_dev *dev = to_sa1111_device(_dev);
0724 
0725     kfree(dev);
0726 }
0727 
0728 static int
0729 sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
0730               struct sa1111_dev_info *info)
0731 {
0732     struct sa1111_dev *dev;
0733     unsigned i;
0734     int ret;
0735 
0736     dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
0737     if (!dev) {
0738         ret = -ENOMEM;
0739         goto err_alloc;
0740     }
0741 
0742     device_initialize(&dev->dev);
0743     dev_set_name(&dev->dev, "%4.4lx", info->offset);
0744     dev->devid   = info->devid;
0745     dev->dev.parent  = sachip->dev;
0746     dev->dev.bus     = &sa1111_bus_type;
0747     dev->dev.release = sa1111_dev_release;
0748     dev->res.start   = sachip->phys + info->offset;
0749     dev->res.end     = dev->res.start + 511;
0750     dev->res.name    = dev_name(&dev->dev);
0751     dev->res.flags   = IORESOURCE_MEM;
0752     dev->mapbase     = sachip->base + info->offset;
0753     dev->skpcr_mask  = info->skpcr_mask;
0754 
0755     for (i = 0; i < ARRAY_SIZE(info->hwirq); i++)
0756         dev->hwirq[i] = info->hwirq[i];
0757 
0758     /*
0759      * If the parent device has a DMA mask associated with it, and
0760      * this child supports DMA, propagate it down to the children.
0761      */
0762     if (info->dma && sachip->dev->dma_mask) {
0763         dev->dma_mask = *sachip->dev->dma_mask;
0764         dev->dev.dma_mask = &dev->dma_mask;
0765         dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
0766     }
0767 
0768     ret = request_resource(parent, &dev->res);
0769     if (ret) {
0770         dev_err(sachip->dev, "failed to allocate resource for %s\n",
0771             dev->res.name);
0772         goto err_resource;
0773     }
0774 
0775     ret = device_add(&dev->dev);
0776     if (ret)
0777         goto err_add;
0778     return 0;
0779 
0780  err_add:
0781     release_resource(&dev->res);
0782  err_resource:
0783     put_device(&dev->dev);
0784  err_alloc:
0785     return ret;
0786 }
0787 
0788 /**
0789  *  sa1111_probe - probe for a single SA1111 chip.
0790  *  @phys_addr: physical address of device.
0791  *
0792  *  Probe for a SA1111 chip.  This must be called
0793  *  before any other SA1111-specific code.
0794  *
0795  *  Returns:
0796  *  %-ENODEV    device not found.
0797  *  %-EBUSY     physical address already marked in-use.
0798  *  %-EINVAL    no platform data passed
0799  *  %0      successful.
0800  */
0801 static int __sa1111_probe(struct device *me, struct resource *mem, int irq)
0802 {
0803     struct sa1111_platform_data *pd = me->platform_data;
0804     struct sa1111 *sachip;
0805     unsigned long id;
0806     unsigned int has_devs;
0807     int i, ret = -ENODEV;
0808 
0809     if (!pd)
0810         return -EINVAL;
0811 
0812     sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL);
0813     if (!sachip)
0814         return -ENOMEM;
0815 
0816     sachip->clk = devm_clk_get(me, "SA1111_CLK");
0817     if (IS_ERR(sachip->clk))
0818         return PTR_ERR(sachip->clk);
0819 
0820     ret = clk_prepare(sachip->clk);
0821     if (ret)
0822         return ret;
0823 
0824     spin_lock_init(&sachip->lock);
0825 
0826     sachip->dev = me;
0827     dev_set_drvdata(sachip->dev, sachip);
0828 
0829     sachip->pdata = pd;
0830     sachip->phys = mem->start;
0831     sachip->irq = irq;
0832 
0833     /*
0834      * Map the whole region.  This also maps the
0835      * registers for our children.
0836      */
0837     sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
0838     if (!sachip->base) {
0839         ret = -ENOMEM;
0840         goto err_clk_unprep;
0841     }
0842 
0843     /*
0844      * Probe for the chip.  Only touch the SBI registers.
0845      */
0846     id = readl_relaxed(sachip->base + SA1111_SKID);
0847     if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
0848         printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
0849         ret = -ENODEV;
0850         goto err_unmap;
0851     }
0852 
0853     pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n",
0854         (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK);
0855 
0856     /*
0857      * We found it.  Wake the chip up, and initialise.
0858      */
0859     sa1111_wake(sachip);
0860 
0861     /*
0862      * The interrupt controller must be initialised before any
0863      * other device to ensure that the interrupts are available.
0864      */
0865     ret = sa1111_setup_irq(sachip, pd->irq_base);
0866     if (ret)
0867         goto err_clk;
0868 
0869     /* Setup the GPIOs - should really be done after the IRQ setup */
0870     ret = sa1111_setup_gpios(sachip);
0871     if (ret)
0872         goto err_irq;
0873 
0874 #ifdef CONFIG_ARCH_SA1100
0875     {
0876     unsigned int val;
0877 
0878     /*
0879      * The SDRAM configuration of the SA1110 and the SA1111 must
0880      * match.  This is very important to ensure that SA1111 accesses
0881      * don't corrupt the SDRAM.  Note that this ungates the SA1111's
0882      * MBGNT signal, so we must have called sa1110_mb_disable()
0883      * beforehand.
0884      */
0885     sa1111_configure_smc(sachip, 1,
0886                  FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
0887                  FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
0888 
0889     /*
0890      * We only need to turn on DCLK whenever we want to use the
0891      * DMA.  It can otherwise be held firmly in the off position.
0892      * (currently, we always enable it.)
0893      */
0894     val = readl_relaxed(sachip->base + SA1111_SKPCR);
0895     writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
0896 
0897     /*
0898      * Enable the SA1110 memory bus request and grant signals.
0899      */
0900     sa1110_mb_enable();
0901     }
0902 #endif
0903 
0904     g_sa1111 = sachip;
0905 
0906     has_devs = ~0;
0907     if (pd)
0908         has_devs &= ~pd->disable_devs;
0909 
0910     for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
0911         if (sa1111_devices[i].devid & has_devs)
0912             sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
0913 
0914     return 0;
0915 
0916  err_irq:
0917     sa1111_remove_irq(sachip);
0918  err_clk:
0919     clk_disable(sachip->clk);
0920  err_unmap:
0921     iounmap(sachip->base);
0922  err_clk_unprep:
0923     clk_unprepare(sachip->clk);
0924     return ret;
0925 }
0926 
0927 static int sa1111_remove_one(struct device *dev, void *data)
0928 {
0929     struct sa1111_dev *sadev = to_sa1111_device(dev);
0930     if (dev->bus != &sa1111_bus_type)
0931         return 0;
0932     device_del(&sadev->dev);
0933     release_resource(&sadev->res);
0934     put_device(&sadev->dev);
0935     return 0;
0936 }
0937 
0938 static void __sa1111_remove(struct sa1111 *sachip)
0939 {
0940     device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
0941 
0942     sa1111_remove_irq(sachip);
0943 
0944     clk_disable(sachip->clk);
0945     clk_unprepare(sachip->clk);
0946 
0947     iounmap(sachip->base);
0948 }
0949 
0950 struct sa1111_save_data {
0951     unsigned int    skcr;
0952     unsigned int    skpcr;
0953     unsigned int    skcdr;
0954     unsigned char   skaud;
0955     unsigned char   skpwm0;
0956     unsigned char   skpwm1;
0957 
0958     /*
0959      * Interrupt controller
0960      */
0961     unsigned int    intpol0;
0962     unsigned int    intpol1;
0963     unsigned int    inten0;
0964     unsigned int    inten1;
0965     unsigned int    wakepol0;
0966     unsigned int    wakepol1;
0967     unsigned int    wakeen0;
0968     unsigned int    wakeen1;
0969 };
0970 
0971 #ifdef CONFIG_PM
0972 
0973 static int sa1111_suspend_noirq(struct device *dev)
0974 {
0975     struct sa1111 *sachip = dev_get_drvdata(dev);
0976     struct sa1111_save_data *save;
0977     unsigned long flags;
0978     unsigned int val;
0979     void __iomem *base;
0980 
0981     save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL);
0982     if (!save)
0983         return -ENOMEM;
0984     sachip->saved_state = save;
0985 
0986     spin_lock_irqsave(&sachip->lock, flags);
0987 
0988     /*
0989      * Save state.
0990      */
0991     base = sachip->base;
0992     save->skcr     = readl_relaxed(base + SA1111_SKCR);
0993     save->skpcr    = readl_relaxed(base + SA1111_SKPCR);
0994     save->skcdr    = readl_relaxed(base + SA1111_SKCDR);
0995     save->skaud    = readl_relaxed(base + SA1111_SKAUD);
0996     save->skpwm0   = readl_relaxed(base + SA1111_SKPWM0);
0997     save->skpwm1   = readl_relaxed(base + SA1111_SKPWM1);
0998 
0999     writel_relaxed(0, sachip->base + SA1111_SKPWM0);
1000     writel_relaxed(0, sachip->base + SA1111_SKPWM1);
1001 
1002     base = sachip->base + SA1111_INTC;
1003     save->intpol0  = readl_relaxed(base + SA1111_INTPOL0);
1004     save->intpol1  = readl_relaxed(base + SA1111_INTPOL1);
1005     save->inten0   = readl_relaxed(base + SA1111_INTEN0);
1006     save->inten1   = readl_relaxed(base + SA1111_INTEN1);
1007     save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0);
1008     save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1);
1009     save->wakeen0  = readl_relaxed(base + SA1111_WAKEEN0);
1010     save->wakeen1  = readl_relaxed(base + SA1111_WAKEEN1);
1011 
1012     /*
1013      * Disable.
1014      */
1015     val = readl_relaxed(sachip->base + SA1111_SKCR);
1016     writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
1017 
1018     clk_disable(sachip->clk);
1019 
1020     spin_unlock_irqrestore(&sachip->lock, flags);
1021 
1022 #ifdef CONFIG_ARCH_SA1100
1023     sa1110_mb_disable();
1024 #endif
1025 
1026     return 0;
1027 }
1028 
1029 /*
1030  *  sa1111_resume - Restore the SA1111 device state.
1031  *  @dev: device to restore
1032  *
1033  *  Restore the general state of the SA1111; clock control and
1034  *  interrupt controller.  Other parts of the SA1111 must be
1035  *  restored by their respective drivers, and must be called
1036  *  via LDM after this function.
1037  */
1038 static int sa1111_resume_noirq(struct device *dev)
1039 {
1040     struct sa1111 *sachip = dev_get_drvdata(dev);
1041     struct sa1111_save_data *save;
1042     unsigned long flags, id;
1043     void __iomem *base;
1044 
1045     save = sachip->saved_state;
1046     if (!save)
1047         return 0;
1048 
1049     /*
1050      * Ensure that the SA1111 is still here.
1051      * FIXME: shouldn't do this here.
1052      */
1053     id = readl_relaxed(sachip->base + SA1111_SKID);
1054     if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
1055         __sa1111_remove(sachip);
1056         dev_set_drvdata(dev, NULL);
1057         kfree(save);
1058         return 0;
1059     }
1060 
1061     /*
1062      * First of all, wake up the chip.
1063      */
1064     sa1111_wake(sachip);
1065 
1066 #ifdef CONFIG_ARCH_SA1100
1067     /* Enable the memory bus request/grant signals */
1068     sa1110_mb_enable();
1069 #endif
1070 
1071     /*
1072      * Only lock for write ops. Also, sa1111_wake must be called with
1073      * released spinlock!
1074      */
1075     spin_lock_irqsave(&sachip->lock, flags);
1076 
1077     writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
1078     writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
1079 
1080     base = sachip->base;
1081     writel_relaxed(save->skcr,     base + SA1111_SKCR);
1082     writel_relaxed(save->skpcr,    base + SA1111_SKPCR);
1083     writel_relaxed(save->skcdr,    base + SA1111_SKCDR);
1084     writel_relaxed(save->skaud,    base + SA1111_SKAUD);
1085     writel_relaxed(save->skpwm0,   base + SA1111_SKPWM0);
1086     writel_relaxed(save->skpwm1,   base + SA1111_SKPWM1);
1087 
1088     base = sachip->base + SA1111_INTC;
1089     writel_relaxed(save->intpol0,  base + SA1111_INTPOL0);
1090     writel_relaxed(save->intpol1,  base + SA1111_INTPOL1);
1091     writel_relaxed(save->inten0,   base + SA1111_INTEN0);
1092     writel_relaxed(save->inten1,   base + SA1111_INTEN1);
1093     writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0);
1094     writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1);
1095     writel_relaxed(save->wakeen0,  base + SA1111_WAKEEN0);
1096     writel_relaxed(save->wakeen1,  base + SA1111_WAKEEN1);
1097 
1098     spin_unlock_irqrestore(&sachip->lock, flags);
1099 
1100     sachip->saved_state = NULL;
1101     kfree(save);
1102 
1103     return 0;
1104 }
1105 
1106 #else
1107 #define sa1111_suspend_noirq NULL
1108 #define sa1111_resume_noirq  NULL
1109 #endif
1110 
1111 static int sa1111_probe(struct platform_device *pdev)
1112 {
1113     struct resource *mem;
1114     int irq;
1115 
1116     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1117     if (!mem)
1118         return -EINVAL;
1119     irq = platform_get_irq(pdev, 0);
1120     if (irq < 0)
1121         return irq;
1122 
1123     return __sa1111_probe(&pdev->dev, mem, irq);
1124 }
1125 
1126 static int sa1111_remove(struct platform_device *pdev)
1127 {
1128     struct sa1111 *sachip = platform_get_drvdata(pdev);
1129 
1130     if (sachip) {
1131 #ifdef CONFIG_PM
1132         kfree(sachip->saved_state);
1133         sachip->saved_state = NULL;
1134 #endif
1135         __sa1111_remove(sachip);
1136         platform_set_drvdata(pdev, NULL);
1137     }
1138 
1139     return 0;
1140 }
1141 
1142 static struct dev_pm_ops sa1111_pm_ops = {
1143     .suspend_noirq = sa1111_suspend_noirq,
1144     .resume_noirq = sa1111_resume_noirq,
1145 };
1146 
1147 /*
1148  *  Not sure if this should be on the system bus or not yet.
1149  *  We really want some way to register a system device at
1150  *  the per-machine level, and then have this driver pick
1151  *  up the registered devices.
1152  *
1153  *  We also need to handle the SDRAM configuration for
1154  *  PXA250/SA1110 machine classes.
1155  */
1156 static struct platform_driver sa1111_device_driver = {
1157     .probe      = sa1111_probe,
1158     .remove     = sa1111_remove,
1159     .driver     = {
1160         .name   = "sa1111",
1161         .pm = &sa1111_pm_ops,
1162     },
1163 };
1164 
1165 /*
1166  *  Get the parent device driver (us) structure
1167  *  from a child function device
1168  */
1169 static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev)
1170 {
1171     return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent);
1172 }
1173 
1174 /*
1175  * The bits in the opdiv field are non-linear.
1176  */
1177 static unsigned char opdiv_table[] = { 1, 4, 2, 8 };
1178 
1179 static unsigned int __sa1111_pll_clock(struct sa1111 *sachip)
1180 {
1181     unsigned int skcdr, fbdiv, ipdiv, opdiv;
1182 
1183     skcdr = readl_relaxed(sachip->base + SA1111_SKCDR);
1184 
1185     fbdiv = (skcdr & 0x007f) + 2;
1186     ipdiv = ((skcdr & 0x0f80) >> 7) + 2;
1187     opdiv = opdiv_table[(skcdr & 0x3000) >> 12];
1188 
1189     return 3686400 * fbdiv / (ipdiv * opdiv);
1190 }
1191 
1192 /**
1193  *  sa1111_pll_clock - return the current PLL clock frequency.
1194  *  @sadev: SA1111 function block
1195  *
1196  *  BUG: we should look at SKCR.  We also blindly believe that
1197  *  the chip is being fed with the 3.6864MHz clock.
1198  *
1199  *  Returns the PLL clock in Hz.
1200  */
1201 unsigned int sa1111_pll_clock(struct sa1111_dev *sadev)
1202 {
1203     struct sa1111 *sachip = sa1111_chip_driver(sadev);
1204 
1205     return __sa1111_pll_clock(sachip);
1206 }
1207 EXPORT_SYMBOL(sa1111_pll_clock);
1208 
1209 /**
1210  *  sa1111_select_audio_mode - select I2S or AC link mode
1211  *  @sadev: SA1111 function block
1212  *  @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S
1213  *
1214  *  Frob the SKCR to select AC Link mode or I2S mode for
1215  *  the audio block.
1216  */
1217 void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode)
1218 {
1219     struct sa1111 *sachip = sa1111_chip_driver(sadev);
1220     unsigned long flags;
1221     unsigned int val;
1222 
1223     spin_lock_irqsave(&sachip->lock, flags);
1224 
1225     val = readl_relaxed(sachip->base + SA1111_SKCR);
1226     if (mode == SA1111_AUDIO_I2S) {
1227         val &= ~SKCR_SELAC;
1228     } else {
1229         val |= SKCR_SELAC;
1230     }
1231     writel_relaxed(val, sachip->base + SA1111_SKCR);
1232 
1233     spin_unlock_irqrestore(&sachip->lock, flags);
1234 }
1235 EXPORT_SYMBOL(sa1111_select_audio_mode);
1236 
1237 /**
1238  *  sa1111_set_audio_rate - set the audio sample rate
1239  *  @sadev: SA1111 SAC function block
1240  *  @rate: sample rate to select
1241  */
1242 int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate)
1243 {
1244     struct sa1111 *sachip = sa1111_chip_driver(sadev);
1245     unsigned int div;
1246 
1247     if (sadev->devid != SA1111_DEVID_SAC)
1248         return -EINVAL;
1249 
1250     div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate;
1251     if (div == 0)
1252         div = 1;
1253     if (div > 128)
1254         div = 128;
1255 
1256     writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
1257 
1258     return 0;
1259 }
1260 EXPORT_SYMBOL(sa1111_set_audio_rate);
1261 
1262 /**
1263  *  sa1111_get_audio_rate - get the audio sample rate
1264  *  @sadev: SA1111 SAC function block device
1265  */
1266 int sa1111_get_audio_rate(struct sa1111_dev *sadev)
1267 {
1268     struct sa1111 *sachip = sa1111_chip_driver(sadev);
1269     unsigned long div;
1270 
1271     if (sadev->devid != SA1111_DEVID_SAC)
1272         return -EINVAL;
1273 
1274     div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1;
1275 
1276     return __sa1111_pll_clock(sachip) / (256 * div);
1277 }
1278 EXPORT_SYMBOL(sa1111_get_audio_rate);
1279 
1280 /*
1281  * Individual device operations.
1282  */
1283 
1284 /**
1285  *  sa1111_enable_device - enable an on-chip SA1111 function block
1286  *  @sadev: SA1111 function block device to enable
1287  */
1288 int sa1111_enable_device(struct sa1111_dev *sadev)
1289 {
1290     struct sa1111 *sachip = sa1111_chip_driver(sadev);
1291     unsigned long flags;
1292     unsigned int val;
1293     int ret = 0;
1294 
1295     if (sachip->pdata && sachip->pdata->enable)
1296         ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
1297 
1298     if (ret == 0) {
1299         spin_lock_irqsave(&sachip->lock, flags);
1300         val = readl_relaxed(sachip->base + SA1111_SKPCR);
1301         writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
1302         spin_unlock_irqrestore(&sachip->lock, flags);
1303     }
1304     return ret;
1305 }
1306 EXPORT_SYMBOL(sa1111_enable_device);
1307 
1308 /**
1309  *  sa1111_disable_device - disable an on-chip SA1111 function block
1310  *  @sadev: SA1111 function block device to disable
1311  */
1312 void sa1111_disable_device(struct sa1111_dev *sadev)
1313 {
1314     struct sa1111 *sachip = sa1111_chip_driver(sadev);
1315     unsigned long flags;
1316     unsigned int val;
1317 
1318     spin_lock_irqsave(&sachip->lock, flags);
1319     val = readl_relaxed(sachip->base + SA1111_SKPCR);
1320     writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
1321     spin_unlock_irqrestore(&sachip->lock, flags);
1322 
1323     if (sachip->pdata && sachip->pdata->disable)
1324         sachip->pdata->disable(sachip->pdata->data, sadev->devid);
1325 }
1326 EXPORT_SYMBOL(sa1111_disable_device);
1327 
1328 int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num)
1329 {
1330     struct sa1111 *sachip = sa1111_chip_driver(sadev);
1331     if (num >= ARRAY_SIZE(sadev->hwirq))
1332         return -EINVAL;
1333     return sa1111_map_irq(sachip, sadev->hwirq[num]);
1334 }
1335 EXPORT_SYMBOL_GPL(sa1111_get_irq);
1336 
1337 /*
1338  *  SA1111 "Register Access Bus."
1339  *
1340  *  We model this as a regular bus type, and hang devices directly
1341  *  off this.
1342  */
1343 static int sa1111_match(struct device *_dev, struct device_driver *_drv)
1344 {
1345     struct sa1111_dev *dev = to_sa1111_device(_dev);
1346     struct sa1111_driver *drv = SA1111_DRV(_drv);
1347 
1348     return !!(dev->devid & drv->devid);
1349 }
1350 
1351 static int sa1111_bus_probe(struct device *dev)
1352 {
1353     struct sa1111_dev *sadev = to_sa1111_device(dev);
1354     struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1355     int ret = -ENODEV;
1356 
1357     if (drv->probe)
1358         ret = drv->probe(sadev);
1359     return ret;
1360 }
1361 
1362 static void sa1111_bus_remove(struct device *dev)
1363 {
1364     struct sa1111_dev *sadev = to_sa1111_device(dev);
1365     struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1366 
1367     if (drv->remove)
1368         drv->remove(sadev);
1369 }
1370 
1371 struct bus_type sa1111_bus_type = {
1372     .name       = "sa1111-rab",
1373     .match      = sa1111_match,
1374     .probe      = sa1111_bus_probe,
1375     .remove     = sa1111_bus_remove,
1376 };
1377 EXPORT_SYMBOL(sa1111_bus_type);
1378 
1379 int sa1111_driver_register(struct sa1111_driver *driver)
1380 {
1381     driver->drv.bus = &sa1111_bus_type;
1382     return driver_register(&driver->drv);
1383 }
1384 EXPORT_SYMBOL(sa1111_driver_register);
1385 
1386 void sa1111_driver_unregister(struct sa1111_driver *driver)
1387 {
1388     driver_unregister(&driver->drv);
1389 }
1390 EXPORT_SYMBOL(sa1111_driver_unregister);
1391 
1392 static int __init sa1111_init(void)
1393 {
1394     int ret = bus_register(&sa1111_bus_type);
1395     if (ret == 0)
1396         platform_driver_register(&sa1111_device_driver);
1397     return ret;
1398 }
1399 
1400 static void __exit sa1111_exit(void)
1401 {
1402     platform_driver_unregister(&sa1111_device_driver);
1403     bus_unregister(&sa1111_bus_type);
1404 }
1405 
1406 subsys_initcall(sa1111_init);
1407 module_exit(sa1111_exit);
1408 
1409 MODULE_DESCRIPTION("Intel Corporation SA1111 core driver");
1410 MODULE_LICENSE("GPL");
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