0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
0004 * Copyright (C) 2017 Alexander Graf <agraf@suse.de>
0005 *
0006 * Based on zynq-zed.dts which is:
0007 * Copyright (C) 2011 - 2014 Xilinx
0008 * Copyright (C) 2012 National Instruments Corp.
0009 *
0010 */
0011
0012 /dts-v1/;
0013 /include/ "zynq-7000.dtsi"
0014
0015 / {
0016 compatible = "xlnx,zynq-7000";
0017
0018 aliases {
0019 ethernet0 = &gem0;
0020 serial0 = &uart1;
0021 serial1 = &uart0;
0022 mmc0 = &sdhci0;
0023 };
0024
0025 memory@0 {
0026 device_type = "memory";
0027 reg = <0x0 0x40000000>;
0028 };
0029
0030 chosen {
0031 stdout-path = "serial0:115200n8";
0032 };
0033
0034 gpio-leds {
0035 compatible = "gpio-leds";
0036 usr-led1 {
0037 label = "usr-led1";
0038 gpios = <&gpio0 0x0 0x1>;
0039 default-state = "off";
0040 };
0041
0042 usr-led2 {
0043 label = "usr-led2";
0044 gpios = <&gpio0 0x9 0x1>;
0045 default-state = "off";
0046 };
0047 };
0048
0049 gpio-keys {
0050 compatible = "gpio-keys";
0051 autorepeat;
0052 key {
0053 label = "K1";
0054 gpios = <&gpio0 0x32 0x1>;
0055 linux,code = <0x66>;
0056 wakeup-source;
0057 autorepeat;
0058 };
0059 };
0060 };
0061
0062 &clkc {
0063 ps-clk-frequency = <33333333>;
0064 };
0065
0066 &gem0 {
0067 status = "okay";
0068 phy-mode = "rgmii-id";
0069 phy-handle = <ðernet_phy>;
0070
0071 ethernet_phy: ethernet-phy@0 {
0072 };
0073 };
0074
0075 &sdhci0 {
0076 status = "okay";
0077 };
0078
0079 &uart0 {
0080 status = "okay";
0081 };
0082
0083 &uart1 {
0084 status = "okay";
0085 };
0086
0087 &usb0 {
0088 status = "okay";
0089 dr_mode = "host";
0090 };
0091
0092 &can0 {
0093 status = "okay";
0094 };
0095
0096 &i2c0 {
0097 status = "okay";
0098 clock-frequency = <400000>;
0099
0100 stlm75@49 {
0101 status = "okay";
0102 compatible = "lm75";
0103 reg = <0x49>;
0104 };
0105
0106 accelerometer@53 {
0107 compatible = "adi,adxl345";
0108 reg = <0x53>;
0109 interrupt-parent = <&intc>;
0110 interrupts = <0x0 0x1e 0x4>;
0111 };
0112 };