boot/dts/zynq-ebaz4205.dts

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2021 Michael Walle <michael@walle.cc>
0004  */
0005 /dts-v1/;
0006 /include/ "zynq-7000.dtsi"
0007
0008 / {
0009         model = "Ebang EBAZ4205";
0010         compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
0011
0012         aliases {
0013                 ethernet0 = &gem0;
0014                 serial0 = &uart1;
0015         };
0016
0017         memory@0 {
0018                 device_type = "memory";
0019                 reg = <0x0 0x10000000>;
0020         };
0021
0022         chosen {
0023                 stdout-path = "serial0:115200n8";
0024         };
0025 };
0026
0027 &clkc {
0028         ps-clk-frequency = <33333333>;
0029         fclk-enable = <8>;
0030 };
0031
0032 &gem0 {
0033         status = "okay";
0034         phy-mode = "mii";
0035         phy-handle = <&phy>;
0036
0037         /* PHY clock */
0038         assigned-clocks = <&clkc 18>;
0039         assigned-clock-rates = <25000000>;
0040
0041         phy: ethernet-phy@0 {
0042                 reg = <0>;
0043         };
0044 };
0045
0046 &gpio0 {
0047         pinctrl-names = "default";
0048         pinctrl-0 = <&pinctrl_gpio0_default>;
0049 };
0050
0051 &nfc0 {
0052         status = "okay";
0053
0054         nand@0 {
0055                 reg = <0>;
0056         };
0057 };
0058
0059 &pinctrl0 {
0060         pinctrl_gpio0_default: gpio0-default {
0061                 mux {
0062                         groups = "gpio0_20_grp", "gpio0_32_grp";
0063                         function = "gpio0";
0064                 };
0065
0066                 conf {
0067                         groups = "gpio0_20_grp", "gpio0_32_grp";
0068                         io-standard = <3>;
0069                         slew-rate = <0>;
0070                 };
0071
0072                 conf-pull-up {
0073                         pins = "MIO20", "MIO32";
0074                         bias-disable;
0075                 };
0076         };
0077
0078         pinctrl_sdhci0_default: sdhci0-default {
0079                 mux {
0080                         groups = "sdio0_2_grp";
0081                         function = "sdio0";
0082                 };
0083
0084                 conf {
0085                         groups = "sdio0_2_grp";
0086                         io-standard = <3>;
0087                         slew-rate = <0>;
0088                         bias-disable;
0089                 };
0090
0091                 mux-cd {
0092                         groups = "gpio0_34_grp";
0093                         function = "sdio0_cd";
0094                 };
0095
0096                 conf-cd {
0097                         groups = "gpio0_34_grp";
0098                         io-standard = <3>;
0099                         slew-rate = <0>;
0100                         bias-high-impedance;
0101                         bias-pull-up;
0102                 };
0103         };
0104
0105         pinctrl_uart1_default: uart1-default {
0106                 mux {
0107                         groups = "uart1_4_grp";
0108                         function = "uart1";
0109                 };
0110
0111                 conf {
0112                         groups = "uart1_4_grp";
0113                         io-standard = <3>;
0114                         slew-rate = <0>;
0115                 };
0116
0117                 conf-rx {
0118                         pins = "MIO25";
0119                         bias-high-impedance;
0120                 };
0121
0122                 conf-tx {
0123                         pins = "MIO24";
0124                         bias-disable;
0125                 };
0126         };
0127 };
0128
0129 &smcc {
0130         status = "okay";
0131 };
0132
0133 &sdhci0 {
0134         status = "okay";
0135         disable-wp;
0136         pinctrl-names = "default";
0137         pinctrl-0 = <&pinctrl_sdhci0_default>;
0138 };
0139
0140 &uart1 {
0141         status = "okay";
0142         pinctrl-names = "default";
0143         pinctrl-0 = <&pinctrl_uart1_default>;
0144 };