0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2011 - 2014 Xilinx
0004 */
0005
0006 / {
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009 compatible = "xlnx,zynq-7000";
0010
0011 cpus {
0012 #address-cells = <1>;
0013 #size-cells = <0>;
0014
0015 cpu0: cpu@0 {
0016 compatible = "arm,cortex-a9";
0017 device_type = "cpu";
0018 reg = <0>;
0019 clocks = <&clkc 3>;
0020 clock-latency = <1000>;
0021 cpu0-supply = <®ulator_vccpint>;
0022 operating-points = <
0023 /* kHz uV */
0024 666667 1000000
0025 333334 1000000
0026 >;
0027 };
0028
0029 cpu1: cpu@1 {
0030 compatible = "arm,cortex-a9";
0031 device_type = "cpu";
0032 reg = <1>;
0033 clocks = <&clkc 3>;
0034 };
0035 };
0036
0037 fpga_full: fpga-full {
0038 compatible = "fpga-region";
0039 fpga-mgr = <&devcfg>;
0040 #address-cells = <1>;
0041 #size-cells = <1>;
0042 ranges;
0043 };
0044
0045 pmu@f8891000 {
0046 compatible = "arm,cortex-a9-pmu";
0047 interrupts = <0 5 4>, <0 6 4>;
0048 interrupt-parent = <&intc>;
0049 reg = <0xf8891000 0x1000>,
0050 <0xf8893000 0x1000>;
0051 };
0052
0053 regulator_vccpint: fixedregulator {
0054 compatible = "regulator-fixed";
0055 regulator-name = "VCCPINT";
0056 regulator-min-microvolt = <1000000>;
0057 regulator-max-microvolt = <1000000>;
0058 regulator-boot-on;
0059 regulator-always-on;
0060 };
0061
0062 replicator {
0063 compatible = "arm,coresight-static-replicator";
0064 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
0065 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
0066
0067 out-ports {
0068 #address-cells = <1>;
0069 #size-cells = <0>;
0070
0071 /* replicator output ports */
0072 port@0 {
0073 reg = <0>;
0074 replicator_out_port0: endpoint {
0075 remote-endpoint = <&tpiu_in_port>;
0076 };
0077 };
0078 port@1 {
0079 reg = <1>;
0080 replicator_out_port1: endpoint {
0081 remote-endpoint = <&etb_in_port>;
0082 };
0083 };
0084 };
0085 in-ports {
0086 /* replicator input port */
0087 port {
0088 replicator_in_port0: endpoint {
0089 remote-endpoint = <&funnel_out_port>;
0090 };
0091 };
0092 };
0093 };
0094
0095 amba: axi {
0096 compatible = "simple-bus";
0097 #address-cells = <1>;
0098 #size-cells = <1>;
0099 interrupt-parent = <&intc>;
0100 ranges;
0101
0102 adc: adc@f8007100 {
0103 compatible = "xlnx,zynq-xadc-1.00.a";
0104 reg = <0xf8007100 0x20>;
0105 interrupts = <0 7 4>;
0106 interrupt-parent = <&intc>;
0107 clocks = <&clkc 12>;
0108 };
0109
0110 can0: can@e0008000 {
0111 compatible = "xlnx,zynq-can-1.0";
0112 status = "disabled";
0113 clocks = <&clkc 19>, <&clkc 36>;
0114 clock-names = "can_clk", "pclk";
0115 reg = <0xe0008000 0x1000>;
0116 interrupts = <0 28 4>;
0117 interrupt-parent = <&intc>;
0118 tx-fifo-depth = <0x40>;
0119 rx-fifo-depth = <0x40>;
0120 };
0121
0122 can1: can@e0009000 {
0123 compatible = "xlnx,zynq-can-1.0";
0124 status = "disabled";
0125 clocks = <&clkc 20>, <&clkc 37>;
0126 clock-names = "can_clk", "pclk";
0127 reg = <0xe0009000 0x1000>;
0128 interrupts = <0 51 4>;
0129 interrupt-parent = <&intc>;
0130 tx-fifo-depth = <0x40>;
0131 rx-fifo-depth = <0x40>;
0132 };
0133
0134 gpio0: gpio@e000a000 {
0135 compatible = "xlnx,zynq-gpio-1.0";
0136 #gpio-cells = <2>;
0137 clocks = <&clkc 42>;
0138 gpio-controller;
0139 interrupt-controller;
0140 #interrupt-cells = <2>;
0141 interrupt-parent = <&intc>;
0142 interrupts = <0 20 4>;
0143 reg = <0xe000a000 0x1000>;
0144 };
0145
0146 i2c0: i2c@e0004000 {
0147 compatible = "cdns,i2c-r1p10";
0148 status = "disabled";
0149 clocks = <&clkc 38>;
0150 interrupt-parent = <&intc>;
0151 interrupts = <0 25 4>;
0152 reg = <0xe0004000 0x1000>;
0153 #address-cells = <1>;
0154 #size-cells = <0>;
0155 };
0156
0157 i2c1: i2c@e0005000 {
0158 compatible = "cdns,i2c-r1p10";
0159 status = "disabled";
0160 clocks = <&clkc 39>;
0161 interrupt-parent = <&intc>;
0162 interrupts = <0 48 4>;
0163 reg = <0xe0005000 0x1000>;
0164 #address-cells = <1>;
0165 #size-cells = <0>;
0166 };
0167
0168 intc: interrupt-controller@f8f01000 {
0169 compatible = "arm,cortex-a9-gic";
0170 #interrupt-cells = <3>;
0171 interrupt-controller;
0172 reg = <0xF8F01000 0x1000>,
0173 <0xF8F00100 0x100>;
0174 };
0175
0176 L2: cache-controller@f8f02000 {
0177 compatible = "arm,pl310-cache";
0178 reg = <0xF8F02000 0x1000>;
0179 interrupts = <0 2 4>;
0180 arm,data-latency = <3 2 2>;
0181 arm,tag-latency = <2 2 2>;
0182 cache-unified;
0183 cache-level = <2>;
0184 };
0185
0186 mc: memory-controller@f8006000 {
0187 compatible = "xlnx,zynq-ddrc-a05";
0188 reg = <0xf8006000 0x1000>;
0189 };
0190
0191 uart0: serial@e0000000 {
0192 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
0193 status = "disabled";
0194 clocks = <&clkc 23>, <&clkc 40>;
0195 clock-names = "uart_clk", "pclk";
0196 reg = <0xE0000000 0x1000>;
0197 interrupts = <0 27 4>;
0198 };
0199
0200 uart1: serial@e0001000 {
0201 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
0202 status = "disabled";
0203 clocks = <&clkc 24>, <&clkc 41>;
0204 clock-names = "uart_clk", "pclk";
0205 reg = <0xE0001000 0x1000>;
0206 interrupts = <0 50 4>;
0207 };
0208
0209 spi0: spi@e0006000 {
0210 compatible = "xlnx,zynq-spi-r1p6";
0211 reg = <0xe0006000 0x1000>;
0212 status = "disabled";
0213 interrupt-parent = <&intc>;
0214 interrupts = <0 26 4>;
0215 clocks = <&clkc 25>, <&clkc 34>;
0216 clock-names = "ref_clk", "pclk";
0217 #address-cells = <1>;
0218 #size-cells = <0>;
0219 };
0220
0221 spi1: spi@e0007000 {
0222 compatible = "xlnx,zynq-spi-r1p6";
0223 reg = <0xe0007000 0x1000>;
0224 status = "disabled";
0225 interrupt-parent = <&intc>;
0226 interrupts = <0 49 4>;
0227 clocks = <&clkc 26>, <&clkc 35>;
0228 clock-names = "ref_clk", "pclk";
0229 #address-cells = <1>;
0230 #size-cells = <0>;
0231 };
0232
0233 gem0: ethernet@e000b000 {
0234 compatible = "cdns,zynq-gem", "cdns,gem";
0235 reg = <0xe000b000 0x1000>;
0236 status = "disabled";
0237 interrupts = <0 22 4>;
0238 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
0239 clock-names = "pclk", "hclk", "tx_clk";
0240 #address-cells = <1>;
0241 #size-cells = <0>;
0242 };
0243
0244 gem1: ethernet@e000c000 {
0245 compatible = "cdns,zynq-gem", "cdns,gem";
0246 reg = <0xe000c000 0x1000>;
0247 status = "disabled";
0248 interrupts = <0 45 4>;
0249 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
0250 clock-names = "pclk", "hclk", "tx_clk";
0251 #address-cells = <1>;
0252 #size-cells = <0>;
0253 };
0254
0255 smcc: memory-controller@e000e000 {
0256 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
0257 reg = <0xe000e000 0x0001000>;
0258 status = "disabled";
0259 clock-names = "memclk", "apb_pclk";
0260 clocks = <&clkc 11>, <&clkc 44>;
0261 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
0262 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
0263 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
0264 #address-cells = <2>;
0265 #size-cells = <1>;
0266
0267 nfc0: nand-controller@0,0 {
0268 compatible = "arm,pl353-nand-r2p1";
0269 reg = <0 0 0x1000000>;
0270 status = "disabled";
0271 #address-cells = <1>;
0272 #size-cells = <0>;
0273 };
0274 };
0275
0276 sdhci0: mmc@e0100000 {
0277 compatible = "arasan,sdhci-8.9a";
0278 status = "disabled";
0279 clock-names = "clk_xin", "clk_ahb";
0280 clocks = <&clkc 21>, <&clkc 32>;
0281 interrupt-parent = <&intc>;
0282 interrupts = <0 24 4>;
0283 reg = <0xe0100000 0x1000>;
0284 };
0285
0286 sdhci1: mmc@e0101000 {
0287 compatible = "arasan,sdhci-8.9a";
0288 status = "disabled";
0289 clock-names = "clk_xin", "clk_ahb";
0290 clocks = <&clkc 22>, <&clkc 33>;
0291 interrupt-parent = <&intc>;
0292 interrupts = <0 47 4>;
0293 reg = <0xe0101000 0x1000>;
0294 };
0295
0296 slcr: slcr@f8000000 {
0297 #address-cells = <1>;
0298 #size-cells = <1>;
0299 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
0300 reg = <0xF8000000 0x1000>;
0301 ranges;
0302 clkc: clkc@100 {
0303 #clock-cells = <1>;
0304 compatible = "xlnx,ps7-clkc";
0305 fclk-enable = <0>;
0306 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
0307 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
0308 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
0309 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
0310 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
0311 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
0312 "gem1_aper", "sdio0_aper", "sdio1_aper",
0313 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
0314 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
0315 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
0316 "dbg_trc", "dbg_apb";
0317 reg = <0x100 0x100>;
0318 };
0319
0320 rstc: rstc@200 {
0321 compatible = "xlnx,zynq-reset";
0322 reg = <0x200 0x48>;
0323 #reset-cells = <1>;
0324 syscon = <&slcr>;
0325 };
0326
0327 pinctrl0: pinctrl@700 {
0328 compatible = "xlnx,pinctrl-zynq";
0329 reg = <0x700 0x200>;
0330 syscon = <&slcr>;
0331 };
0332 };
0333
0334 dmac_s: dmac@f8003000 {
0335 compatible = "arm,pl330", "arm,primecell";
0336 reg = <0xf8003000 0x1000>;
0337 interrupt-parent = <&intc>;
0338 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
0339 "dma4", "dma5", "dma6", "dma7";
0340 interrupts = <0 13 4>,
0341 <0 14 4>, <0 15 4>,
0342 <0 16 4>, <0 17 4>,
0343 <0 40 4>, <0 41 4>,
0344 <0 42 4>, <0 43 4>;
0345 #dma-cells = <1>;
0346 clocks = <&clkc 27>;
0347 clock-names = "apb_pclk";
0348 };
0349
0350 devcfg: devcfg@f8007000 {
0351 compatible = "xlnx,zynq-devcfg-1.0";
0352 reg = <0xf8007000 0x100>;
0353 interrupt-parent = <&intc>;
0354 interrupts = <0 8 4>;
0355 clocks = <&clkc 12>;
0356 clock-names = "ref_clk";
0357 syscon = <&slcr>;
0358 };
0359
0360 global_timer: timer@f8f00200 {
0361 compatible = "arm,cortex-a9-global-timer";
0362 reg = <0xf8f00200 0x20>;
0363 interrupts = <1 11 0x301>;
0364 interrupt-parent = <&intc>;
0365 clocks = <&clkc 4>;
0366 };
0367
0368 ttc0: timer@f8001000 {
0369 interrupt-parent = <&intc>;
0370 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
0371 compatible = "cdns,ttc";
0372 clocks = <&clkc 6>;
0373 reg = <0xF8001000 0x1000>;
0374 };
0375
0376 ttc1: timer@f8002000 {
0377 interrupt-parent = <&intc>;
0378 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
0379 compatible = "cdns,ttc";
0380 clocks = <&clkc 6>;
0381 reg = <0xF8002000 0x1000>;
0382 };
0383
0384 scutimer: timer@f8f00600 {
0385 interrupt-parent = <&intc>;
0386 interrupts = <1 13 0x301>;
0387 compatible = "arm,cortex-a9-twd-timer";
0388 reg = <0xf8f00600 0x20>;
0389 clocks = <&clkc 4>;
0390 };
0391
0392 usb0: usb@e0002000 {
0393 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
0394 status = "disabled";
0395 clocks = <&clkc 28>;
0396 interrupt-parent = <&intc>;
0397 interrupts = <0 21 4>;
0398 reg = <0xe0002000 0x1000>;
0399 phy_type = "ulpi";
0400 };
0401
0402 usb1: usb@e0003000 {
0403 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
0404 status = "disabled";
0405 clocks = <&clkc 29>;
0406 interrupt-parent = <&intc>;
0407 interrupts = <0 44 4>;
0408 reg = <0xe0003000 0x1000>;
0409 phy_type = "ulpi";
0410 };
0411
0412 watchdog0: watchdog@f8005000 {
0413 clocks = <&clkc 45>;
0414 compatible = "cdns,wdt-r1p2";
0415 interrupt-parent = <&intc>;
0416 interrupts = <0 9 1>;
0417 reg = <0xf8005000 0x1000>;
0418 timeout-sec = <10>;
0419 };
0420
0421 etb@f8801000 {
0422 compatible = "arm,coresight-etb10", "arm,primecell";
0423 reg = <0xf8801000 0x1000>;
0424 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
0425 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
0426 in-ports {
0427 port {
0428 etb_in_port: endpoint {
0429 remote-endpoint = <&replicator_out_port1>;
0430 };
0431 };
0432 };
0433 };
0434
0435 tpiu@f8803000 {
0436 compatible = "arm,coresight-tpiu", "arm,primecell";
0437 reg = <0xf8803000 0x1000>;
0438 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
0439 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
0440 in-ports {
0441 port {
0442 tpiu_in_port: endpoint {
0443 remote-endpoint = <&replicator_out_port0>;
0444 };
0445 };
0446 };
0447 };
0448
0449 funnel@f8804000 {
0450 compatible = "arm,coresight-static-funnel", "arm,primecell";
0451 reg = <0xf8804000 0x1000>;
0452 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
0453 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
0454
0455 /* funnel output ports */
0456 out-ports {
0457 port {
0458 funnel_out_port: endpoint {
0459 remote-endpoint =
0460 <&replicator_in_port0>;
0461 };
0462 };
0463 };
0464
0465 in-ports {
0466 #address-cells = <1>;
0467 #size-cells = <0>;
0468
0469 /* funnel input ports */
0470 port@0 {
0471 reg = <0>;
0472 funnel0_in_port0: endpoint {
0473 remote-endpoint = <&ptm0_out_port>;
0474 };
0475 };
0476
0477 port@1 {
0478 reg = <1>;
0479 funnel0_in_port1: endpoint {
0480 remote-endpoint = <&ptm1_out_port>;
0481 };
0482 };
0483
0484 port@2 {
0485 reg = <2>;
0486 funnel0_in_port2: endpoint {
0487 };
0488 };
0489 /* The other input ports are not connect to anything */
0490 };
0491 };
0492
0493 ptm@f889c000 {
0494 compatible = "arm,coresight-etm3x", "arm,primecell";
0495 reg = <0xf889c000 0x1000>;
0496 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
0497 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
0498 cpu = <&cpu0>;
0499 out-ports {
0500 port {
0501 ptm0_out_port: endpoint {
0502 remote-endpoint = <&funnel0_in_port0>;
0503 };
0504 };
0505 };
0506 };
0507
0508 ptm@f889d000 {
0509 compatible = "arm,coresight-etm3x", "arm,primecell";
0510 reg = <0xf889d000 0x1000>;
0511 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
0512 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
0513 cpu = <&cpu1>;
0514 out-ports {
0515 port {
0516 ptm1_out_port: endpoint {
0517 remote-endpoint = <&funnel0_in_port1>;
0518 };
0519 };
0520 };
0521 };
0522 };
0523 };
