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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
0004 *
0005 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
0006 */
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 compatible = "wm,wm8850";
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016
0017 cpu@0 {
0018 device_type = "cpu";
0019 compatible = "arm,cortex-a9";
0020 reg = <0x0>;
0021 };
0022 };
0023
0024 memory {
0025 device_type = "memory";
0026 reg = <0x0 0x0>;
0027 };
0028
0029 aliases {
0030 serial0 = &uart0;
0031 serial1 = &uart1;
0032 serial2 = &uart2;
0033 serial3 = &uart3;
0034 };
0035
0036 soc {
0037 #address-cells = <1>;
0038 #size-cells = <1>;
0039 compatible = "simple-bus";
0040 ranges;
0041 interrupt-parent = <&intc0>;
0042
0043 intc0: interrupt-controller@d8140000 {
0044 compatible = "via,vt8500-intc";
0045 interrupt-controller;
0046 reg = <0xd8140000 0x10000>;
0047 #interrupt-cells = <1>;
0048 };
0049
0050 /* Secondary IC cascaded to intc0 */
0051 intc1: interrupt-controller@d8150000 {
0052 compatible = "via,vt8500-intc";
0053 interrupt-controller;
0054 #interrupt-cells = <1>;
0055 reg = <0xD8150000 0x10000>;
0056 interrupts = <56 57 58 59 60 61 62 63>;
0057 };
0058
0059 pinctrl: pinctrl@d8110000 {
0060 compatible = "wm,wm8850-pinctrl";
0061 reg = <0xd8110000 0x10000>;
0062 interrupt-controller;
0063 #interrupt-cells = <2>;
0064 gpio-controller;
0065 #gpio-cells = <2>;
0066 };
0067
0068 pmc@d8130000 {
0069 compatible = "via,vt8500-pmc";
0070 reg = <0xd8130000 0x1000>;
0071
0072 clocks {
0073 #address-cells = <1>;
0074 #size-cells = <0>;
0075
0076 ref25: ref25M {
0077 #clock-cells = <0>;
0078 compatible = "fixed-clock";
0079 clock-frequency = <25000000>;
0080 };
0081
0082 ref24: ref24M {
0083 #clock-cells = <0>;
0084 compatible = "fixed-clock";
0085 clock-frequency = <24000000>;
0086 };
0087
0088 plla: plla {
0089 #clock-cells = <0>;
0090 compatible = "wm,wm8850-pll-clock";
0091 clocks = <&ref24>;
0092 reg = <0x200>;
0093 };
0094
0095 pllb: pllb {
0096 #clock-cells = <0>;
0097 compatible = "wm,wm8850-pll-clock";
0098 clocks = <&ref24>;
0099 reg = <0x204>;
0100 };
0101
0102 pllc: pllc {
0103 #clock-cells = <0>;
0104 compatible = "wm,wm8850-pll-clock";
0105 clocks = <&ref24>;
0106 reg = <0x208>;
0107 };
0108
0109 plld: plld {
0110 #clock-cells = <0>;
0111 compatible = "wm,wm8850-pll-clock";
0112 clocks = <&ref24>;
0113 reg = <0x20c>;
0114 };
0115
0116 plle: plle {
0117 #clock-cells = <0>;
0118 compatible = "wm,wm8850-pll-clock";
0119 clocks = <&ref24>;
0120 reg = <0x210>;
0121 };
0122
0123 pllf: pllf {
0124 #clock-cells = <0>;
0125 compatible = "wm,wm8850-pll-clock";
0126 clocks = <&ref24>;
0127 reg = <0x214>;
0128 };
0129
0130 pllg: pllg {
0131 #clock-cells = <0>;
0132 compatible = "wm,wm8850-pll-clock";
0133 clocks = <&ref24>;
0134 reg = <0x218>;
0135 };
0136
0137 clkarm: arm {
0138 #clock-cells = <0>;
0139 compatible = "via,vt8500-device-clock";
0140 clocks = <&plla>;
0141 divisor-reg = <0x300>;
0142 };
0143
0144 clkahb: ahb {
0145 #clock-cells = <0>;
0146 compatible = "via,vt8500-device-clock";
0147 clocks = <&pllb>;
0148 divisor-reg = <0x304>;
0149 };
0150
0151 clkapb: apb {
0152 #clock-cells = <0>;
0153 compatible = "via,vt8500-device-clock";
0154 clocks = <&pllb>;
0155 divisor-reg = <0x320>;
0156 };
0157
0158 clkddr: ddr {
0159 #clock-cells = <0>;
0160 compatible = "via,vt8500-device-clock";
0161 clocks = <&plld>;
0162 divisor-reg = <0x310>;
0163 };
0164
0165 clkuart0: uart0 {
0166 #clock-cells = <0>;
0167 compatible = "via,vt8500-device-clock";
0168 clocks = <&ref24>;
0169 enable-reg = <0x254>;
0170 enable-bit = <24>;
0171 };
0172
0173 clkuart1: uart1 {
0174 #clock-cells = <0>;
0175 compatible = "via,vt8500-device-clock";
0176 clocks = <&ref24>;
0177 enable-reg = <0x254>;
0178 enable-bit = <25>;
0179 };
0180
0181 clkuart2: uart2 {
0182 #clock-cells = <0>;
0183 compatible = "via,vt8500-device-clock";
0184 clocks = <&ref24>;
0185 enable-reg = <0x254>;
0186 enable-bit = <26>;
0187 };
0188
0189 clkuart3: uart3 {
0190 #clock-cells = <0>;
0191 compatible = "via,vt8500-device-clock";
0192 clocks = <&ref24>;
0193 enable-reg = <0x254>;
0194 enable-bit = <27>;
0195 };
0196
0197 clkpwm: pwm {
0198 #clock-cells = <0>;
0199 compatible = "via,vt8500-device-clock";
0200 clocks = <&pllb>;
0201 divisor-reg = <0x350>;
0202 enable-reg = <0x250>;
0203 enable-bit = <17>;
0204 };
0205
0206 clksdhc: sdhc {
0207 #clock-cells = <0>;
0208 compatible = "via,vt8500-device-clock";
0209 clocks = <&pllb>;
0210 divisor-reg = <0x330>;
0211 divisor-mask = <0x3f>;
0212 enable-reg = <0x250>;
0213 enable-bit = <0>;
0214 };
0215 };
0216 };
0217
0218 fb: fb@d8051700 {
0219 compatible = "wm,wm8505-fb";
0220 reg = <0xd8051700 0x200>;
0221 };
0222
0223 ge_rops@d8050400 {
0224 compatible = "wm,prizm-ge-rops";
0225 reg = <0xd8050400 0x100>;
0226 };
0227
0228 pwm: pwm@d8220000 {
0229 #pwm-cells = <3>;
0230 compatible = "via,vt8500-pwm";
0231 reg = <0xd8220000 0x100>;
0232 clocks = <&clkpwm>;
0233 };
0234
0235 timer@d8130100 {
0236 compatible = "via,vt8500-timer";
0237 reg = <0xd8130100 0x28>;
0238 interrupts = <36>;
0239 };
0240
0241 ehci@d8007900 {
0242 compatible = "via,vt8500-ehci";
0243 reg = <0xd8007900 0x200>;
0244 interrupts = <26>;
0245 };
0246
0247 uhci@d8007b00 {
0248 compatible = "platform-uhci";
0249 reg = <0xd8007b00 0x200>;
0250 interrupts = <26>;
0251 };
0252
0253 uhci@d8008d00 {
0254 compatible = "platform-uhci";
0255 reg = <0xd8008d00 0x200>;
0256 interrupts = <26>;
0257 };
0258
0259 uart0: serial@d8200000 {
0260 compatible = "via,vt8500-uart";
0261 reg = <0xd8200000 0x1040>;
0262 interrupts = <32>;
0263 clocks = <&clkuart0>;
0264 status = "disabled";
0265 };
0266
0267 uart1: serial@d82b0000 {
0268 compatible = "via,vt8500-uart";
0269 reg = <0xd82b0000 0x1040>;
0270 interrupts = <33>;
0271 clocks = <&clkuart1>;
0272 status = "disabled";
0273 };
0274
0275 uart2: serial@d8210000 {
0276 compatible = "via,vt8500-uart";
0277 reg = <0xd8210000 0x1040>;
0278 interrupts = <47>;
0279 clocks = <&clkuart2>;
0280 status = "disabled";
0281 };
0282
0283 uart3: serial@d82c0000 {
0284 compatible = "via,vt8500-uart";
0285 reg = <0xd82c0000 0x1040>;
0286 interrupts = <50>;
0287 clocks = <&clkuart3>;
0288 status = "disabled";
0289 };
0290
0291 rtc@d8100000 {
0292 compatible = "via,vt8500-rtc";
0293 reg = <0xd8100000 0x10000>;
0294 interrupts = <48>;
0295 };
0296
0297 sdhc@d800a000 {
0298 compatible = "wm,wm8505-sdhc";
0299 reg = <0xd800a000 0x1000>;
0300 interrupts = <20 21>;
0301 clocks = <&clksdhc>;
0302 bus-width = <4>;
0303 sdon-inverted;
0304 };
0305
0306 ethernet@d8004000 {
0307 compatible = "via,vt8500-rhine";
0308 reg = <0xd8004000 0x100>;
0309 interrupts = <10>;
0310 };
0311 };
0312 };
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