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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
0004 *
0005 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
0006 */
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 compatible = "wm,wm8750";
0012
0013 cpus {
0014 #address-cells = <0>;
0015 #size-cells = <0>;
0016
0017 cpu {
0018 device_type = "cpu";
0019 compatible = "arm,arm1176jzf";
0020 };
0021 };
0022
0023 memory {
0024 device_type = "memory";
0025 reg = <0x0 0x0>;
0026 };
0027
0028 aliases {
0029 serial0 = &uart0;
0030 serial1 = &uart1;
0031 serial2 = &uart2;
0032 serial3 = &uart3;
0033 serial4 = &uart4;
0034 serial5 = &uart5;
0035 i2c0 = &i2c_0;
0036 i2c1 = &i2c_1;
0037 };
0038
0039 soc {
0040 #address-cells = <1>;
0041 #size-cells = <1>;
0042 compatible = "simple-bus";
0043 ranges;
0044 interrupt-parent = <&intc0>;
0045
0046 intc0: interrupt-controller@d8140000 {
0047 compatible = "via,vt8500-intc";
0048 interrupt-controller;
0049 reg = <0xd8140000 0x10000>;
0050 #interrupt-cells = <1>;
0051 };
0052
0053 /* Secondary IC cascaded to intc0 */
0054 intc1: interrupt-controller@d8150000 {
0055 compatible = "via,vt8500-intc";
0056 interrupt-controller;
0057 #interrupt-cells = <1>;
0058 reg = <0xD8150000 0x10000>;
0059 interrupts = <56 57 58 59 60 61 62 63>;
0060 };
0061
0062 pinctrl: pinctrl@d8110000 {
0063 compatible = "wm,wm8750-pinctrl";
0064 reg = <0xd8110000 0x10000>;
0065 interrupt-controller;
0066 #interrupt-cells = <2>;
0067 gpio-controller;
0068 #gpio-cells = <2>;
0069 };
0070
0071 pmc@d8130000 {
0072 compatible = "via,vt8500-pmc";
0073 reg = <0xd8130000 0x1000>;
0074
0075 clocks {
0076 #address-cells = <1>;
0077 #size-cells = <0>;
0078
0079 ref24: ref24M {
0080 #clock-cells = <0>;
0081 compatible = "fixed-clock";
0082 clock-frequency = <24000000>;
0083 };
0084
0085 ref25: ref25M {
0086 #clock-cells = <0>;
0087 compatible = "fixed-clock";
0088 clock-frequency = <25000000>;
0089 };
0090
0091 plla: plla {
0092 #clock-cells = <0>;
0093 compatible = "wm,wm8750-pll-clock";
0094 clocks = <&ref25>;
0095 reg = <0x200>;
0096 };
0097
0098 pllb: pllb {
0099 #clock-cells = <0>;
0100 compatible = "wm,wm8750-pll-clock";
0101 clocks = <&ref25>;
0102 reg = <0x204>;
0103 };
0104
0105 pllc: pllc {
0106 #clock-cells = <0>;
0107 compatible = "wm,wm8750-pll-clock";
0108 clocks = <&ref25>;
0109 reg = <0x208>;
0110 };
0111
0112 plld: plld {
0113 #clock-cells = <0>;
0114 compatible = "wm,wm8750-pll-clock";
0115 clocks = <&ref25>;
0116 reg = <0x20C>;
0117 };
0118
0119 plle: plle {
0120 #clock-cells = <0>;
0121 compatible = "wm,wm8750-pll-clock";
0122 clocks = <&ref25>;
0123 reg = <0x210>;
0124 };
0125
0126 clkarm: arm {
0127 #clock-cells = <0>;
0128 compatible = "via,vt8500-device-clock";
0129 clocks = <&plla>;
0130 divisor-reg = <0x300>;
0131 };
0132
0133 clkahb: ahb {
0134 #clock-cells = <0>;
0135 compatible = "via,vt8500-device-clock";
0136 clocks = <&pllb>;
0137 divisor-reg = <0x304>;
0138 };
0139
0140 clkapb: apb {
0141 #clock-cells = <0>;
0142 compatible = "via,vt8500-device-clock";
0143 clocks = <&pllb>;
0144 divisor-reg = <0x320>;
0145 };
0146
0147 clkddr: ddr {
0148 #clock-cells = <0>;
0149 compatible = "via,vt8500-device-clock";
0150 clocks = <&plld>;
0151 divisor-reg = <0x310>;
0152 };
0153
0154 clkuart0: uart0 {
0155 #clock-cells = <0>;
0156 compatible = "via,vt8500-device-clock";
0157 clocks = <&ref24>;
0158 enable-reg = <0x254>;
0159 enable-bit = <24>;
0160 };
0161
0162 clkuart1: uart1 {
0163 #clock-cells = <0>;
0164 compatible = "via,vt8500-device-clock";
0165 clocks = <&ref24>;
0166 enable-reg = <0x254>;
0167 enable-bit = <25>;
0168 };
0169
0170 clkuart2: uart2 {
0171 #clock-cells = <0>;
0172 compatible = "via,vt8500-device-clock";
0173 clocks = <&ref24>;
0174 enable-reg = <0x254>;
0175 enable-bit = <26>;
0176 };
0177
0178 clkuart3: uart3 {
0179 #clock-cells = <0>;
0180 compatible = "via,vt8500-device-clock";
0181 clocks = <&ref24>;
0182 enable-reg = <0x254>;
0183 enable-bit = <27>;
0184 };
0185
0186 clkuart4: uart4 {
0187 #clock-cells = <0>;
0188 compatible = "via,vt8500-device-clock";
0189 clocks = <&ref24>;
0190 enable-reg = <0x254>;
0191 enable-bit = <28>;
0192 };
0193
0194 clkuart5: uart5 {
0195 #clock-cells = <0>;
0196 compatible = "via,vt8500-device-clock";
0197 clocks = <&ref24>;
0198 enable-reg = <0x254>;
0199 enable-bit = <29>;
0200 };
0201
0202 clkpwm: pwm {
0203 #clock-cells = <0>;
0204 compatible = "via,vt8500-device-clock";
0205 clocks = <&pllb>;
0206 divisor-reg = <0x350>;
0207 enable-reg = <0x250>;
0208 enable-bit = <17>;
0209 };
0210
0211 clksdhc: sdhc {
0212 #clock-cells = <0>;
0213 compatible = "via,vt8500-device-clock";
0214 clocks = <&pllb>;
0215 divisor-reg = <0x330>;
0216 divisor-mask = <0x3f>;
0217 enable-reg = <0x250>;
0218 enable-bit = <0>;
0219 };
0220
0221 clki2c0: i2c0clk {
0222 #clock-cells = <0>;
0223 compatible = "via,vt8500-device-clock";
0224 clocks = <&pllb>;
0225 divisor-reg = <0x3A0>;
0226 enable-reg = <0x250>;
0227 enable-bit = <8>;
0228 };
0229
0230 clki2c1: i2c1clk {
0231 #clock-cells = <0>;
0232 compatible = "via,vt8500-device-clock";
0233 clocks = <&pllb>;
0234 divisor-reg = <0x3A4>;
0235 enable-reg = <0x250>;
0236 enable-bit = <9>;
0237 };
0238 };
0239 };
0240
0241 pwm: pwm@d8220000 {
0242 #pwm-cells = <3>;
0243 compatible = "via,vt8500-pwm";
0244 reg = <0xd8220000 0x100>;
0245 clocks = <&clkpwm>;
0246 };
0247
0248 timer@d8130100 {
0249 compatible = "via,vt8500-timer";
0250 reg = <0xd8130100 0x28>;
0251 interrupts = <36>;
0252 };
0253
0254 ehci@d8007900 {
0255 compatible = "via,vt8500-ehci";
0256 reg = <0xd8007900 0x200>;
0257 interrupts = <26>;
0258 };
0259
0260 uhci@d8007b00 {
0261 compatible = "platform-uhci";
0262 reg = <0xd8007b00 0x200>;
0263 interrupts = <26>;
0264 };
0265
0266 uhci@d8008d00 {
0267 compatible = "platform-uhci";
0268 reg = <0xd8008d00 0x200>;
0269 interrupts = <26>;
0270 };
0271
0272 uart0: serial@d8200000 {
0273 compatible = "via,vt8500-uart";
0274 reg = <0xd8200000 0x1040>;
0275 interrupts = <32>;
0276 clocks = <&clkuart0>;
0277 status = "disabled";
0278 };
0279
0280 uart1: serial@d82b0000 {
0281 compatible = "via,vt8500-uart";
0282 reg = <0xd82b0000 0x1040>;
0283 interrupts = <33>;
0284 clocks = <&clkuart1>;
0285 status = "disabled";
0286 };
0287
0288 uart2: serial@d8210000 {
0289 compatible = "via,vt8500-uart";
0290 reg = <0xd8210000 0x1040>;
0291 interrupts = <47>;
0292 clocks = <&clkuart2>;
0293 status = "disabled";
0294 };
0295
0296 uart3: serial@d82c0000 {
0297 compatible = "via,vt8500-uart";
0298 reg = <0xd82c0000 0x1040>;
0299 interrupts = <50>;
0300 clocks = <&clkuart3>;
0301 status = "disabled";
0302 };
0303
0304 uart4: serial@d8370000 {
0305 compatible = "via,vt8500-uart";
0306 reg = <0xd8370000 0x1040>;
0307 interrupts = <30>;
0308 clocks = <&clkuart4>;
0309 status = "disabled";
0310 };
0311
0312 uart5: serial@d8380000 {
0313 compatible = "via,vt8500-uart";
0314 reg = <0xd8380000 0x1040>;
0315 interrupts = <43>;
0316 clocks = <&clkuart5>;
0317 status = "disabled";
0318 };
0319
0320 rtc@d8100000 {
0321 compatible = "via,vt8500-rtc";
0322 reg = <0xd8100000 0x10000>;
0323 interrupts = <48>;
0324 };
0325
0326 sdhc@d800a000 {
0327 compatible = "wm,wm8505-sdhc";
0328 reg = <0xd800a000 0x1000>;
0329 interrupts = <20 21>;
0330 clocks = <&clksdhc>;
0331 bus-width = <4>;
0332 sdon-inverted;
0333 };
0334
0335 i2c_0: i2c@d8280000 {
0336 compatible = "wm,wm8505-i2c";
0337 reg = <0xd8280000 0x1000>;
0338 interrupts = <19>;
0339 clocks = <&clki2c0>;
0340 clock-frequency = <400000>;
0341 };
0342
0343 i2c_1: i2c@d8320000 {
0344 compatible = "wm,wm8505-i2c";
0345 reg = <0xd8320000 0x1000>;
0346 interrupts = <18>;
0347 clocks = <&clki2c1>;
0348 clock-frequency = <400000>;
0349 };
0350 };
0351 };
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