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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
0004 *
0005 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
0006 */
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 compatible = "wm,wm8650";
0012
0013 cpus {
0014 #address-cells = <0>;
0015 #size-cells = <0>;
0016
0017 cpu {
0018 device_type = "cpu";
0019 compatible = "arm,arm926ej-s";
0020 };
0021 };
0022
0023 memory {
0024 device_type = "memory";
0025 reg = <0x0 0x0>;
0026 };
0027
0028 aliases {
0029 serial0 = &uart0;
0030 serial1 = &uart1;
0031 };
0032
0033 soc {
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 compatible = "simple-bus";
0037 ranges;
0038 interrupt-parent = <&intc0>;
0039
0040 intc0: interrupt-controller@d8140000 {
0041 compatible = "via,vt8500-intc";
0042 interrupt-controller;
0043 reg = <0xd8140000 0x10000>;
0044 #interrupt-cells = <1>;
0045 };
0046
0047 /* Secondary IC cascaded to intc0 */
0048 intc1: interrupt-controller@d8150000 {
0049 compatible = "via,vt8500-intc";
0050 interrupt-controller;
0051 #interrupt-cells = <1>;
0052 reg = <0xD8150000 0x10000>;
0053 interrupts = <56 57 58 59 60 61 62 63>;
0054 };
0055
0056 pinctrl: pinctrl@d8110000 {
0057 compatible = "wm,wm8650-pinctrl";
0058 reg = <0xd8110000 0x10000>;
0059 interrupt-controller;
0060 #interrupt-cells = <2>;
0061 gpio-controller;
0062 #gpio-cells = <2>;
0063 };
0064
0065 pmc@d8130000 {
0066 compatible = "via,vt8500-pmc";
0067 reg = <0xd8130000 0x1000>;
0068
0069 clocks {
0070 #address-cells = <1>;
0071 #size-cells = <0>;
0072
0073 ref25: ref25M {
0074 #clock-cells = <0>;
0075 compatible = "fixed-clock";
0076 clock-frequency = <25000000>;
0077 };
0078
0079 ref24: ref24M {
0080 #clock-cells = <0>;
0081 compatible = "fixed-clock";
0082 clock-frequency = <24000000>;
0083 };
0084
0085 plla: plla {
0086 #clock-cells = <0>;
0087 compatible = "wm,wm8650-pll-clock";
0088 clocks = <&ref25>;
0089 reg = <0x200>;
0090 };
0091
0092 pllb: pllb {
0093 #clock-cells = <0>;
0094 compatible = "wm,wm8650-pll-clock";
0095 clocks = <&ref25>;
0096 reg = <0x204>;
0097 };
0098
0099 pllc: pllc {
0100 #clock-cells = <0>;
0101 compatible = "wm,wm8650-pll-clock";
0102 clocks = <&ref25>;
0103 reg = <0x208>;
0104 };
0105
0106 plld: plld {
0107 #clock-cells = <0>;
0108 compatible = "wm,wm8650-pll-clock";
0109 clocks = <&ref25>;
0110 reg = <0x20c>;
0111 };
0112
0113 plle: plle {
0114 #clock-cells = <0>;
0115 compatible = "wm,wm8650-pll-clock";
0116 clocks = <&ref25>;
0117 reg = <0x210>;
0118 };
0119
0120 clkarm: arm {
0121 #clock-cells = <0>;
0122 compatible = "via,vt8500-device-clock";
0123 clocks = <&plla>;
0124 divisor-reg = <0x300>;
0125 };
0126
0127 clkahb: ahb {
0128 #clock-cells = <0>;
0129 compatible = "via,vt8500-device-clock";
0130 clocks = <&pllb>;
0131 divisor-reg = <0x304>;
0132 };
0133
0134 clkapb: apb {
0135 #clock-cells = <0>;
0136 compatible = "via,vt8500-device-clock";
0137 clocks = <&pllb>;
0138 divisor-reg = <0x320>;
0139 };
0140
0141 clkddr: ddr {
0142 #clock-cells = <0>;
0143 compatible = "via,vt8500-device-clock";
0144 clocks = <&plld>;
0145 divisor-reg = <0x310>;
0146 };
0147
0148 clkuart0: uart0 {
0149 #clock-cells = <0>;
0150 compatible = "via,vt8500-device-clock";
0151 clocks = <&ref24>;
0152 enable-reg = <0x250>;
0153 enable-bit = <1>;
0154 };
0155
0156 clkuart1: uart1 {
0157 #clock-cells = <0>;
0158 compatible = "via,vt8500-device-clock";
0159 clocks = <&ref24>;
0160 enable-reg = <0x250>;
0161 enable-bit = <2>;
0162 };
0163
0164 clksdhc: sdhc {
0165 #clock-cells = <0>;
0166 compatible = "via,vt8500-device-clock";
0167 clocks = <&pllb>;
0168 divisor-reg = <0x328>;
0169 divisor-mask = <0x3f>;
0170 enable-reg = <0x254>;
0171 enable-bit = <18>;
0172 };
0173 };
0174 };
0175
0176 timer@d8130100 {
0177 compatible = "via,vt8500-timer";
0178 reg = <0xd8130100 0x28>;
0179 interrupts = <36>;
0180 };
0181
0182 ehci@d8007900 {
0183 compatible = "via,vt8500-ehci";
0184 reg = <0xd8007900 0x200>;
0185 interrupts = <43>;
0186 };
0187
0188 uhci@d8007b00 {
0189 compatible = "platform-uhci";
0190 reg = <0xd8007b00 0x200>;
0191 interrupts = <43>;
0192 };
0193
0194 sdhc@d800a000 {
0195 compatible = "wm,wm8505-sdhc";
0196 reg = <0xd800a000 0x400>;
0197 interrupts = <20>, <21>;
0198 clocks = <&clksdhc>;
0199 bus-width = <4>;
0200 sdon-inverted;
0201 };
0202
0203 fb: fb@d8050800 {
0204 compatible = "wm,wm8505-fb";
0205 reg = <0xd8050800 0x200>;
0206 };
0207
0208 ge_rops@d8050400 {
0209 compatible = "wm,prizm-ge-rops";
0210 reg = <0xd8050400 0x100>;
0211 };
0212
0213 uart0: serial@d8200000 {
0214 compatible = "via,vt8500-uart";
0215 reg = <0xd8200000 0x1040>;
0216 interrupts = <32>;
0217 clocks = <&clkuart0>;
0218 status = "disabled";
0219 };
0220
0221 uart1: serial@d82b0000 {
0222 compatible = "via,vt8500-uart";
0223 reg = <0xd82b0000 0x1040>;
0224 interrupts = <33>;
0225 clocks = <&clkuart1>;
0226 status = "disabled";
0227 };
0228
0229 rtc@d8100000 {
0230 compatible = "via,vt8500-rtc";
0231 reg = <0xd8100000 0x10000>;
0232 interrupts = <48>;
0233 };
0234
0235 ethernet@d8004000 {
0236 compatible = "via,vt8500-rhine";
0237 reg = <0xd8004000 0x100>;
0238 interrupts = <10>;
0239 };
0240 };
0241 };
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