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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
0004 *
0005 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
0006 */
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 compatible = "wm,wm8505";
0012
0013 cpus {
0014 #address-cells = <0>;
0015 #size-cells = <0>;
0016
0017 cpu {
0018 device_type = "cpu";
0019 compatible = "arm,arm926ej-s";
0020 };
0021 };
0022
0023 memory {
0024 device_type = "memory";
0025 reg = <0x0 0x0>;
0026 };
0027
0028 aliases {
0029 serial0 = &uart0;
0030 serial1 = &uart1;
0031 serial2 = &uart2;
0032 serial3 = &uart3;
0033 serial4 = &uart4;
0034 serial5 = &uart5;
0035 };
0036
0037 soc {
0038 #address-cells = <1>;
0039 #size-cells = <1>;
0040 compatible = "simple-bus";
0041 ranges;
0042 interrupt-parent = <&intc0>;
0043
0044 intc0: interrupt-controller@d8140000 {
0045 compatible = "via,vt8500-intc";
0046 interrupt-controller;
0047 reg = <0xd8140000 0x10000>;
0048 #interrupt-cells = <1>;
0049 };
0050
0051 /* Secondary IC cascaded to intc0 */
0052 intc1: interrupt-controller@d8150000 {
0053 compatible = "via,vt8500-intc";
0054 interrupt-controller;
0055 #interrupt-cells = <1>;
0056 reg = <0xD8150000 0x10000>;
0057 interrupts = <56 57 58 59 60 61 62 63>;
0058 };
0059
0060 pinctrl: pinctrl@d8110000 {
0061 compatible = "wm,wm8505-pinctrl";
0062 reg = <0xd8110000 0x10000>;
0063 interrupt-controller;
0064 #interrupt-cells = <2>;
0065 gpio-controller;
0066 #gpio-cells = <2>;
0067 };
0068
0069 pmc@d8130000 {
0070 compatible = "via,vt8500-pmc";
0071 reg = <0xd8130000 0x1000>;
0072 clocks {
0073 #address-cells = <1>;
0074 #size-cells = <0>;
0075
0076 ref24: ref24M {
0077 #clock-cells = <0>;
0078 compatible = "fixed-clock";
0079 clock-frequency = <24000000>;
0080 };
0081
0082 ref25: ref25M {
0083 #clock-cells = <0>;
0084 compatible = "fixed-clock";
0085 clock-frequency = <25000000>;
0086 };
0087
0088 plla: plla {
0089 #clock-cells = <0>;
0090 compatible = "via,vt8500-pll-clock";
0091 clocks = <&ref25>;
0092 reg = <0x200>;
0093 };
0094
0095 pllb: pllb {
0096 #clock-cells = <0>;
0097 compatible = "via,vt8500-pll-clock";
0098 clocks = <&ref25>;
0099 reg = <0x204>;
0100 };
0101
0102 pllc: pllc {
0103 #clock-cells = <0>;
0104 compatible = "via,vt8500-pll-clock";
0105 clocks = <&ref25>;
0106 reg = <0x208>;
0107 };
0108
0109 plld: plld {
0110 #clock-cells = <0>;
0111 compatible = "via,vt8500-pll-clock";
0112 clocks = <&ref25>;
0113 reg = <0x20c>;
0114 };
0115
0116 clkarm: arm {
0117 #clock-cells = <0>;
0118 compatible = "via,vt8500-device-clock";
0119 clocks = <&plla>;
0120 divisor-reg = <0x300>;
0121 };
0122
0123 clkahb: ahb {
0124 #clock-cells = <0>;
0125 compatible = "via,vt8500-device-clock";
0126 clocks = <&pllb>;
0127 divisor-reg = <0x304>;
0128 };
0129
0130 clkapb: apb {
0131 #clock-cells = <0>;
0132 compatible = "via,vt8500-device-clock";
0133 clocks = <&pllb>;
0134 divisor-reg = <0x350>;
0135 };
0136
0137 clkddr: ddr {
0138 #clock-cells = <0>;
0139 compatible = "via,vt8500-device-clock";
0140 clocks = <&plld>;
0141 divisor-reg = <0x310>;
0142 };
0143
0144 clkuart0: uart0 {
0145 #clock-cells = <0>;
0146 compatible = "via,vt8500-device-clock";
0147 clocks = <&ref24>;
0148 enable-reg = <0x250>;
0149 enable-bit = <1>;
0150 };
0151
0152 clkuart1: uart1 {
0153 #clock-cells = <0>;
0154 compatible = "via,vt8500-device-clock";
0155 clocks = <&ref24>;
0156 enable-reg = <0x250>;
0157 enable-bit = <2>;
0158 };
0159
0160 clkuart2: uart2 {
0161 #clock-cells = <0>;
0162 compatible = "via,vt8500-device-clock";
0163 clocks = <&ref24>;
0164 enable-reg = <0x250>;
0165 enable-bit = <3>;
0166 };
0167
0168 clkuart3: uart3 {
0169 #clock-cells = <0>;
0170 compatible = "via,vt8500-device-clock";
0171 clocks = <&ref24>;
0172 enable-reg = <0x250>;
0173 enable-bit = <4>;
0174 };
0175
0176 clkuart4: uart4 {
0177 #clock-cells = <0>;
0178 compatible = "via,vt8500-device-clock";
0179 clocks = <&ref24>;
0180 enable-reg = <0x250>;
0181 enable-bit = <22>;
0182 };
0183
0184 clkuart5: uart5 {
0185 #clock-cells = <0>;
0186 compatible = "via,vt8500-device-clock";
0187 clocks = <&ref24>;
0188 enable-reg = <0x250>;
0189 enable-bit = <23>;
0190 };
0191
0192 clksdhc: sdhc {
0193 #clock-cells = <0>;
0194 compatible = "via,vt8500-device-clock";
0195 clocks = <&pllb>;
0196 divisor-reg = <0x328>;
0197 divisor-mask = <0x3f>;
0198 enable-reg = <0x254>;
0199 enable-bit = <18>;
0200 };
0201 };
0202 };
0203
0204 timer@d8130100 {
0205 compatible = "via,vt8500-timer";
0206 reg = <0xd8130100 0x28>;
0207 interrupts = <36>;
0208 };
0209
0210 ehci@d8007100 {
0211 compatible = "via,vt8500-ehci";
0212 reg = <0xd8007100 0x200>;
0213 interrupts = <1>;
0214 };
0215
0216 uhci@d8007300 {
0217 compatible = "platform-uhci";
0218 reg = <0xd8007300 0x200>;
0219 interrupts = <0>;
0220 };
0221
0222 fb: fb@d8050800 {
0223 compatible = "wm,wm8505-fb";
0224 reg = <0xd8050800 0x200>;
0225 };
0226
0227 ge_rops@d8050400 {
0228 compatible = "wm,prizm-ge-rops";
0229 reg = <0xd8050400 0x100>;
0230 };
0231
0232 uart0: serial@d8200000 {
0233 compatible = "via,vt8500-uart";
0234 reg = <0xd8200000 0x1040>;
0235 interrupts = <32>;
0236 clocks = <&clkuart0>;
0237 status = "disabled";
0238 };
0239
0240 uart1: serial@d82b0000 {
0241 compatible = "via,vt8500-uart";
0242 reg = <0xd82b0000 0x1040>;
0243 interrupts = <33>;
0244 clocks = <&clkuart1>;
0245 status = "disabled";
0246 };
0247
0248 uart2: serial@d8210000 {
0249 compatible = "via,vt8500-uart";
0250 reg = <0xd8210000 0x1040>;
0251 interrupts = <47>;
0252 clocks = <&clkuart2>;
0253 status = "disabled";
0254 };
0255
0256 uart3: serial@d82c0000 {
0257 compatible = "via,vt8500-uart";
0258 reg = <0xd82c0000 0x1040>;
0259 interrupts = <50>;
0260 clocks = <&clkuart3>;
0261 status = "disabled";
0262 };
0263
0264 uart4: serial@d8370000 {
0265 compatible = "via,vt8500-uart";
0266 reg = <0xd8370000 0x1040>;
0267 interrupts = <31>;
0268 clocks = <&clkuart4>;
0269 status = "disabled";
0270 };
0271
0272 uart5: serial@d8380000 {
0273 compatible = "via,vt8500-uart";
0274 reg = <0xd8380000 0x1040>;
0275 interrupts = <30>;
0276 clocks = <&clkuart5>;
0277 status = "disabled";
0278 };
0279
0280 rtc@d8100000 {
0281 compatible = "via,vt8500-rtc";
0282 reg = <0xd8100000 0x10000>;
0283 interrupts = <48>;
0284 };
0285
0286 sdhc@d800a000 {
0287 compatible = "wm,wm8505-sdhc";
0288 reg = <0xd800a000 0x400>;
0289 interrupts = <20>, <21>;
0290 clocks = <&clksdhc>;
0291 bus-width = <4>;
0292 };
0293 };
0294 };
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