0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002
0003 /*
0004 * Device tree file for ZII's SSMB SPU3 board
0005 *
0006 * SSMB - SPU3 Switch Management Board
0007 * SPU - Seat Power Unit
0008 *
0009 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
0010 *
0011 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
0012 * Freescale Semiconductor, Inc.
0013 */
0014
0015 /dts-v1/;
0016 #include "vf610.dtsi"
0017
0018 / {
0019 model = "ZII VF610 SSMB SPU3 Board";
0020 compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
0021
0022 chosen {
0023 stdout-path = &uart0;
0024 };
0025
0026 memory@80000000 {
0027 device_type = "memory";
0028 reg = <0x80000000 0x20000000>;
0029 };
0030
0031 gpio-leds {
0032 compatible = "gpio-leds";
0033 pinctrl-0 = <&pinctrl_leds_debug>;
0034 pinctrl-names = "default";
0035
0036 led-debug {
0037 label = "zii:green:debug1";
0038 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
0039 linux,default-trigger = "heartbeat";
0040 };
0041 };
0042
0043 reg_vcc_3v3_mcu: regulator {
0044 compatible = "regulator-fixed";
0045 regulator-name = "vcc_3v3_mcu";
0046 regulator-min-microvolt = <3300000>;
0047 regulator-max-microvolt = <3300000>;
0048 };
0049
0050 supply-voltage-monitor {
0051 compatible = "iio-hwmon";
0052 io-channels = <&adc0 8>, /* 12V_MAIN */
0053 <&adc0 9>, /* +3.3V */
0054 <&adc1 8>, /* VCC_1V5 */
0055 <&adc1 9>; /* VCC_1V2 */
0056 };
0057 };
0058
0059 &adc0 {
0060 vref-supply = <®_vcc_3v3_mcu>;
0061 status = "okay";
0062 };
0063
0064 &adc1 {
0065 vref-supply = <®_vcc_3v3_mcu>;
0066 status = "okay";
0067 };
0068
0069 &dspi1 {
0070 bus-num = <1>;
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&pinctrl_dspi1>;
0073 /*
0074 * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
0075 * node disabled by default and rely on bootloader to enable
0076 * it when appropriate.
0077 */
0078 status = "disabled";
0079
0080 flash@0 {
0081 #address-cells = <1>;
0082 #size-cells = <1>;
0083 compatible = "m25p128", "jedec,spi-nor";
0084 reg = <0>;
0085 spi-max-frequency = <50000000>;
0086
0087 partition@0 {
0088 label = "m25p128-0";
0089 reg = <0x0 0x01000000>;
0090 };
0091 };
0092 };
0093
0094 &edma0 {
0095 status = "okay";
0096 };
0097
0098 &edma1 {
0099 status = "okay";
0100 };
0101
0102 &esdhc0 {
0103 pinctrl-names = "default";
0104 pinctrl-0 = <&pinctrl_esdhc0>;
0105 bus-width = <8>;
0106 non-removable;
0107 no-1-8-v;
0108 keep-power-in-suspend;
0109 no-sdio;
0110 no-sd;
0111 status = "okay";
0112 };
0113
0114 &esdhc1 {
0115 pinctrl-names = "default";
0116 pinctrl-0 = <&pinctrl_esdhc1>;
0117 bus-width = <4>;
0118 no-sdio;
0119 status = "okay";
0120 };
0121
0122 &fec1 {
0123 phy-mode = "rmii";
0124 pinctrl-names = "default";
0125 pinctrl-0 = <&pinctrl_fec1>;
0126 status = "okay";
0127
0128 fixed-link {
0129 speed = <100>;
0130 full-duplex;
0131 };
0132
0133 mdio1: mdio {
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136 clock-frequency = <12500000>;
0137 suppress-preamble;
0138 status = "okay";
0139
0140 switch0: switch0@0 {
0141 compatible = "marvell,mv88e6190";
0142 pinctrl-0 = <&pinctrl_gpio_switch0>;
0143 pinctrl-names = "default";
0144 reg = <0>;
0145 eeprom-length = <65536>;
0146 interrupt-parent = <&gpio3>;
0147 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0148 interrupt-controller;
0149 #interrupt-cells = <2>;
0150
0151 ports {
0152 #address-cells = <1>;
0153 #size-cells = <0>;
0154
0155 port@0 {
0156 reg = <0>;
0157 label = "cpu";
0158 ethernet = <&fec1>;
0159
0160 fixed-link {
0161 speed = <100>;
0162 full-duplex;
0163 };
0164 };
0165
0166 port@1 {
0167 reg = <1>;
0168 label = "eth_cu_1000_1";
0169 };
0170
0171 port@2 {
0172 reg = <2>;
0173 label = "eth_cu_1000_2";
0174 };
0175
0176 port@3 {
0177 reg = <3>;
0178 label = "eth_cu_1000_3";
0179 };
0180
0181 port@4 {
0182 reg = <4>;
0183 label = "eth_cu_1000_4";
0184 };
0185
0186 port@5 {
0187 reg = <5>;
0188 label = "eth_cu_1000_5";
0189 };
0190
0191 port@6 {
0192 reg = <6>;
0193 label = "eth_cu_1000_6";
0194 };
0195 };
0196 };
0197 };
0198 };
0199
0200 &i2c0 {
0201 clock-frequency = <100000>;
0202 pinctrl-names = "default";
0203 pinctrl-0 = <&pinctrl_i2c0>;
0204 status = "okay";
0205
0206 gpio6: io-expander@22 {
0207 compatible = "nxp,pca9554";
0208 reg = <0x22>;
0209 gpio-controller;
0210 #gpio-cells = <2>;
0211 };
0212
0213 lm75@48 {
0214 compatible = "national,lm75";
0215 reg = <0x48>;
0216 };
0217
0218 eeprom@50 {
0219 compatible = "atmel,24c04";
0220 reg = <0x50>;
0221 label = "nameplate";
0222 };
0223
0224 eeprom@52 {
0225 compatible = "atmel,24c04";
0226 reg = <0x52>;
0227 };
0228 };
0229
0230 &i2c1 {
0231 clock-frequency = <100000>;
0232 pinctrl-names = "default";
0233 pinctrl-0 = <&pinctrl_i2c1>;
0234 status = "okay";
0235
0236 watchdog@38 {
0237 compatible = "zii,rave-wdt";
0238 reg = <0x38>;
0239 };
0240 };
0241
0242 &snvsrtc {
0243 status = "disabled";
0244 };
0245
0246 &uart0 {
0247 pinctrl-names = "default";
0248 pinctrl-0 = <&pinctrl_uart0>;
0249 status = "okay";
0250 };
0251
0252 &uart1 {
0253 pinctrl-names = "default";
0254 pinctrl-0 = <&pinctrl_uart1>;
0255 status = "okay";
0256
0257 rave-sp {
0258 compatible = "zii,rave-sp-rdu2";
0259 current-speed = <1000000>;
0260 #address-cells = <1>;
0261 #size-cells = <1>;
0262
0263 watchdog {
0264 compatible = "zii,rave-sp-watchdog";
0265 };
0266
0267 eeprom@a3 {
0268 compatible = "zii,rave-sp-eeprom";
0269 reg = <0xa3 0x4000>;
0270 #address-cells = <1>;
0271 #size-cells = <1>;
0272 zii,eeprom-name = "main-eeprom";
0273 };
0274 };
0275 };
0276
0277 &wdoga5 {
0278 status = "disabled";
0279 };
0280
0281 &iomuxc {
0282 pinctrl_dspi1: dspi1grp {
0283 fsl,pins = <
0284 VF610_PAD_PTD5__DSPI1_CS0 0x1182
0285 VF610_PAD_PTD4__DSPI1_CS1 0x1182
0286 VF610_PAD_PTC6__DSPI1_SIN 0x1181
0287 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
0288 VF610_PAD_PTC8__DSPI1_SCK 0x1182
0289 >;
0290 };
0291
0292 pinctrl_esdhc0: esdhc0grp {
0293 fsl,pins = <
0294 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
0295 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
0296 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
0297 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
0298 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
0299 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
0300 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
0301 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
0302 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
0303 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
0304 >;
0305 };
0306
0307 pinctrl_esdhc1: esdhc1grp {
0308 fsl,pins = <
0309 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
0310 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
0311 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
0312 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
0313 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
0314 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
0315 >;
0316 };
0317
0318 pinctrl_fec1: fec1grp {
0319 fsl,pins = <
0320 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
0321 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
0322 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
0323 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
0324 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
0325 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
0326 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
0327 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
0328 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
0329 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
0330 >;
0331 };
0332
0333 pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
0334 fsl,pins = <
0335 VF610_PAD_PTB28__GPIO_98 0x219d
0336 >;
0337 };
0338
0339 pinctrl_i2c0: i2c0grp {
0340 fsl,pins = <
0341 VF610_PAD_PTB14__I2C0_SCL 0x37ff
0342 VF610_PAD_PTB15__I2C0_SDA 0x37ff
0343 >;
0344 };
0345
0346 pinctrl_i2c1: i2c1grp {
0347 fsl,pins = <
0348 VF610_PAD_PTB16__I2C1_SCL 0x37ff
0349 VF610_PAD_PTB17__I2C1_SDA 0x37ff
0350 >;
0351 };
0352
0353 pinctrl_leds_debug: pinctrl-leds-debug {
0354 fsl,pins = <
0355 VF610_PAD_PTD3__GPIO_82 0x31c2
0356 >;
0357 };
0358
0359 pinctrl_uart0: uart0grp {
0360 fsl,pins = <
0361 VF610_PAD_PTB10__UART0_TX 0x21a2
0362 VF610_PAD_PTB11__UART0_RX 0x21a1
0363 >;
0364 };
0365
0366 pinctrl_uart1: uart1grp {
0367 fsl,pins = <
0368 VF610_PAD_PTB23__UART1_TX 0x21a2
0369 VF610_PAD_PTB24__UART1_RX 0x21a1
0370 >;
0371 };
0372 };
