0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002
0003 /*
0004 * Device tree file for ZII's SSMB DTU board
0005 *
0006 * SSMB - SPU3 Switch Management Board
0007 * DTU - Digital Tapping Unit
0008 *
0009 * Copyright (C) 2015-2019 Zodiac Inflight Innovations
0010 *
0011 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
0012 * Freescale Semiconductor, Inc.
0013 */
0014
0015 /dts-v1/;
0016 #include "vf610.dtsi"
0017
0018 / {
0019 model = "ZII VF610 SSMB DTU Board";
0020 compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610";
0021
0022 chosen {
0023 stdout-path = &uart0;
0024 };
0025
0026 memory@80000000 {
0027 device_type = "memory";
0028 reg = <0x80000000 0x20000000>;
0029 };
0030
0031 gpio-leds {
0032 compatible = "gpio-leds";
0033 pinctrl-0 = <&pinctrl_leds_debug>;
0034 pinctrl-names = "default";
0035
0036 led-debug {
0037 label = "zii:green:debug1";
0038 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
0039 linux,default-trigger = "heartbeat";
0040 };
0041 };
0042
0043 reg_vcc_3v3_mcu: regulator {
0044 compatible = "regulator-fixed";
0045 regulator-name = "vcc_3v3_mcu";
0046 regulator-min-microvolt = <3300000>;
0047 regulator-max-microvolt = <3300000>;
0048 };
0049
0050 supply-voltage-monitor {
0051 compatible = "iio-hwmon";
0052 io-channels = <&adc0 8>, /* 12V_MAIN */
0053 <&adc0 9>, /* +3.3V */
0054 <&adc1 8>, /* VCC_1V5 */
0055 <&adc1 9>; /* VCC_1V2 */
0056 };
0057 };
0058
0059 &adc0 {
0060 vref-supply = <®_vcc_3v3_mcu>;
0061 status = "okay";
0062 };
0063
0064 &adc1 {
0065 vref-supply = <®_vcc_3v3_mcu>;
0066 status = "okay";
0067 };
0068
0069 &edma0 {
0070 status = "okay";
0071 };
0072
0073 &edma1 {
0074 status = "okay";
0075 };
0076
0077 &esdhc0 {
0078 pinctrl-names = "default";
0079 pinctrl-0 = <&pinctrl_esdhc0>;
0080 bus-width = <8>;
0081 non-removable;
0082 no-1-8-v;
0083 keep-power-in-suspend;
0084 no-sdio;
0085 no-sd;
0086 status = "okay";
0087 };
0088
0089 &esdhc1 {
0090 pinctrl-names = "default";
0091 pinctrl-0 = <&pinctrl_esdhc1>;
0092 bus-width = <4>;
0093 no-sdio;
0094 status = "okay";
0095 };
0096
0097 &fec1 {
0098 phy-mode = "rmii";
0099 pinctrl-names = "default";
0100 pinctrl-0 = <&pinctrl_fec1>;
0101 status = "okay";
0102
0103 fixed-link {
0104 speed = <100>;
0105 full-duplex;
0106 };
0107
0108 mdio1: mdio {
0109 #address-cells = <1>;
0110 #size-cells = <0>;
0111 clock-frequency = <12500000>;
0112 suppress-preamble;
0113 status = "okay";
0114
0115 switch0: switch0@0 {
0116 compatible = "marvell,mv88e6190";
0117 pinctrl-0 = <&pinctrl_gpio_switch0>;
0118 pinctrl-names = "default";
0119 reg = <0>;
0120 eeprom-length = <65536>;
0121 interrupt-parent = <&gpio3>;
0122 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0123 interrupt-controller;
0124 #interrupt-cells = <2>;
0125
0126 ports {
0127 #address-cells = <1>;
0128 #size-cells = <0>;
0129
0130 port@0 {
0131 reg = <0>;
0132 label = "cpu";
0133 ethernet = <&fec1>;
0134
0135 fixed-link {
0136 speed = <100>;
0137 full-duplex;
0138 };
0139 };
0140
0141 port@1 {
0142 reg = <1>;
0143 label = "eth_cu_100_3";
0144 };
0145
0146 port@5 {
0147 reg = <5>;
0148 label = "eth_cu_1000_4";
0149 };
0150
0151 port@6 {
0152 reg = <6>;
0153 label = "eth_cu_1000_5";
0154 };
0155
0156 port@8 {
0157 reg = <8>;
0158 label = "eth_cu_1000_1";
0159 };
0160
0161 port@9 {
0162 reg = <9>;
0163 label = "eth_cu_1000_2";
0164 phy-handle = <&phy9>;
0165 phy-mode = "sgmii";
0166 managed = "in-band-status";
0167 };
0168 };
0169
0170 mdio1 {
0171 compatible = "marvell,mv88e6xxx-mdio-external";
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174
0175 phy9: phy9@0 {
0176 compatible = "ethernet-phy-ieee802.3-c45";
0177 pinctrl-0 = <&pinctrl_gpio_phy9>;
0178 pinctrl-names = "default";
0179 interrupt-parent = <&gpio2>;
0180 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
0181 reg = <0>;
0182 };
0183 };
0184 };
0185 };
0186 };
0187
0188 &i2c0 {
0189 clock-frequency = <100000>;
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&pinctrl_i2c0>;
0192 status = "okay";
0193
0194 gpio6: gpio-expander@22 {
0195 compatible = "nxp,pca9554";
0196 reg = <0x22>;
0197 gpio-controller;
0198 #gpio-cells = <2>;
0199 };
0200
0201 /* On SSMB */
0202 temperature-sensor@48 {
0203 compatible = "national,lm75";
0204 reg = <0x48>;
0205 };
0206
0207 /* On DSB */
0208 temperature-sensor@4d {
0209 compatible = "national,lm75";
0210 reg = <0x4d>;
0211 };
0212
0213 eeprom@50 {
0214 compatible = "atmel,24c04";
0215 reg = <0x50>;
0216 label = "nameplate";
0217 };
0218
0219 eeprom@52 {
0220 compatible = "atmel,24c04";
0221 reg = <0x52>;
0222 };
0223 };
0224
0225 &snvsrtc {
0226 status = "disabled";
0227 };
0228
0229 &uart0 {
0230 pinctrl-names = "default";
0231 pinctrl-0 = <&pinctrl_uart0>;
0232 status = "okay";
0233 };
0234
0235 &iomuxc {
0236 pinctrl_dspi1: dspi1grp {
0237 fsl,pins = <
0238 VF610_PAD_PTD5__DSPI1_CS0 0x1182
0239 VF610_PAD_PTD4__DSPI1_CS1 0x1182
0240 VF610_PAD_PTC6__DSPI1_SIN 0x1181
0241 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
0242 VF610_PAD_PTC8__DSPI1_SCK 0x1182
0243 >;
0244 };
0245
0246 pinctrl_esdhc0: esdhc0grp {
0247 fsl,pins = <
0248 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
0249 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
0250 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
0251 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
0252 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
0253 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
0254 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
0255 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
0256 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
0257 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
0258 >;
0259 };
0260
0261 pinctrl_esdhc1: esdhc1grp {
0262 fsl,pins = <
0263 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
0264 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
0265 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
0266 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
0267 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
0268 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
0269 >;
0270 };
0271
0272 pinctrl_fec1: fec1grp {
0273 fsl,pins = <
0274 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
0275 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
0276 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
0277 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
0278 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
0279 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
0280 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
0281 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
0282 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
0283 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
0284 >;
0285 };
0286
0287 pinctrl_gpio_phy9: pinctrl-gpio-phy9 {
0288 fsl,pins = <
0289 VF610_PAD_PTB24__GPIO_94 0x219d
0290 >;
0291 };
0292
0293 pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
0294 fsl,pins = <
0295 VF610_PAD_PTB28__GPIO_98 0x219d
0296 >;
0297 };
0298
0299 pinctrl_i2c0: i2c0grp {
0300 fsl,pins = <
0301 VF610_PAD_PTB14__I2C0_SCL 0x37ff
0302 VF610_PAD_PTB15__I2C0_SDA 0x37ff
0303 >;
0304 };
0305
0306 pinctrl_i2c1: i2c1grp {
0307 fsl,pins = <
0308 VF610_PAD_PTB16__I2C1_SCL 0x37ff
0309 VF610_PAD_PTB17__I2C1_SDA 0x37ff
0310 >;
0311 };
0312
0313 pinctrl_leds_debug: pinctrl-leds-debug {
0314 fsl,pins = <
0315 VF610_PAD_PTD3__GPIO_82 0x31c2
0316 >;
0317 };
0318
0319 pinctrl_uart0: uart0grp {
0320 fsl,pins = <
0321 VF610_PAD_PTB10__UART0_TX 0x21a2
0322 VF610_PAD_PTB11__UART0_RX 0x21a1
0323 >;
0324 };
0325 };
