0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002
0003 /*
0004 * Device tree file for ZII's SPB4 board
0005 *
0006 * SPB - Seat Power Box
0007 *
0008 * Copyright (C) 2019 Zodiac Inflight Innovations
0009 */
0010
0011 /dts-v1/;
0012 #include "vf610.dtsi"
0013
0014 / {
0015 model = "ZII VF610 SPB4 Board";
0016 compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";
0017
0018 chosen {
0019 stdout-path = &uart0;
0020 };
0021
0022 memory@80000000 {
0023 device_type = "memory";
0024 reg = <0x80000000 0x20000000>;
0025 };
0026
0027 gpio-leds {
0028 compatible = "gpio-leds";
0029 pinctrl-0 = <&pinctrl_leds_debug>;
0030 pinctrl-names = "default";
0031
0032 led-debug {
0033 label = "zii:green:debug1";
0034 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
0035 linux,default-trigger = "heartbeat";
0036 };
0037 };
0038
0039 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
0040 compatible = "regulator-fixed";
0041 regulator-name = "vcc_3v3_mcu";
0042 regulator-min-microvolt = <3300000>;
0043 regulator-max-microvolt = <3300000>;
0044 };
0045
0046 supply-voltage-monitor {
0047 compatible = "iio-hwmon";
0048 io-channels = <&adc0 8>, /* 28V_SW */
0049 <&adc0 9>, /* +3.3V */
0050 <&adc1 8>, /* VCC_1V5 */
0051 <&adc1 9>; /* VCC_1V2 */
0052 };
0053 };
0054
0055 &adc0 {
0056 vref-supply = <®_vcc_3v3_mcu>;
0057 status = "okay";
0058 };
0059
0060 &adc1 {
0061 vref-supply = <®_vcc_3v3_mcu>;
0062 status = "okay";
0063 };
0064
0065 &dspi1 {
0066 bus-num = <1>;
0067 pinctrl-names = "default";
0068 pinctrl-0 = <&pinctrl_dspi1>;
0069 status = "okay";
0070
0071 flash@0 {
0072 #address-cells = <1>;
0073 #size-cells = <1>;
0074 compatible = "m25p128", "jedec,spi-nor";
0075 reg = <0>;
0076 spi-max-frequency = <50000000>;
0077 };
0078 };
0079
0080 &edma0 {
0081 status = "okay";
0082 };
0083
0084 &edma1 {
0085 status = "okay";
0086 };
0087
0088 &esdhc0 {
0089 pinctrl-names = "default";
0090 pinctrl-0 = <&pinctrl_esdhc0>;
0091 bus-width = <8>;
0092 non-removable;
0093 no-1-8-v;
0094 keep-power-in-suspend;
0095 no-sdio;
0096 no-sd;
0097 status = "okay";
0098 };
0099
0100 &esdhc1 {
0101 pinctrl-names = "default";
0102 pinctrl-0 = <&pinctrl_esdhc1>;
0103 bus-width = <4>;
0104 no-sdio;
0105 status = "okay";
0106 };
0107
0108 &fec1 {
0109 phy-mode = "rmii";
0110 pinctrl-names = "default";
0111 pinctrl-0 = <&pinctrl_fec1>;
0112 status = "okay";
0113
0114 fixed-link {
0115 speed = <100>;
0116 full-duplex;
0117 };
0118
0119 mdio1: mdio {
0120 #address-cells = <1>;
0121 #size-cells = <0>;
0122 clock-frequency = <12500000>;
0123 suppress-preamble;
0124 status = "okay";
0125
0126 switch0: switch0@0 {
0127 compatible = "marvell,mv88e6190";
0128 pinctrl-0 = <&pinctrl_gpio_switch0>;
0129 pinctrl-names = "default";
0130 reg = <0>;
0131 eeprom-length = <65536>;
0132 interrupt-parent = <&gpio3>;
0133 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0134 interrupt-controller;
0135 #interrupt-cells = <2>;
0136
0137 ports {
0138 #address-cells = <1>;
0139 #size-cells = <0>;
0140
0141 port@0 {
0142 reg = <0>;
0143 label = "cpu";
0144 ethernet = <&fec1>;
0145
0146 fixed-link {
0147 speed = <100>;
0148 full-duplex;
0149 };
0150 };
0151
0152 port@1 {
0153 reg = <1>;
0154 label = "eth_cu_1000_1";
0155 };
0156
0157 port@2 {
0158 reg = <2>;
0159 label = "eth_cu_1000_2";
0160 };
0161
0162 port@3 {
0163 reg = <3>;
0164 label = "eth_cu_1000_3";
0165 };
0166
0167 port@4 {
0168 reg = <4>;
0169 label = "eth_cu_1000_4";
0170 };
0171
0172 port@5 {
0173 reg = <5>;
0174 label = "eth_cu_1000_5";
0175 };
0176
0177 port@6 {
0178 reg = <6>;
0179 label = "eth_cu_1000_6";
0180 };
0181 };
0182 };
0183 };
0184 };
0185
0186 &i2c0 {
0187 clock-frequency = <100000>;
0188 pinctrl-names = "default";
0189 pinctrl-0 = <&pinctrl_i2c0>;
0190 status = "okay";
0191
0192 io-expander@22 {
0193 compatible = "nxp,pca9554";
0194 reg = <0x22>;
0195 gpio-controller;
0196 #gpio-cells = <2>;
0197 };
0198
0199 eeprom@50 {
0200 compatible = "atmel,24c04";
0201 reg = <0x50>;
0202 label = "nameplate";
0203 };
0204
0205 eeprom@52 {
0206 compatible = "atmel,24c04";
0207 reg = <0x52>;
0208 };
0209 };
0210
0211 &i2c1 {
0212 clock-frequency = <100000>;
0213 pinctrl-names = "default";
0214 pinctrl-0 = <&pinctrl_i2c1>;
0215 status = "okay";
0216
0217 watchdog@38 {
0218 compatible = "zii,rave-wdt";
0219 reg = <0x38>;
0220 };
0221 };
0222
0223 &snvsrtc {
0224 status = "disabled";
0225 };
0226
0227 &uart0 {
0228 pinctrl-names = "default";
0229 pinctrl-0 = <&pinctrl_uart0>;
0230 status = "okay";
0231 };
0232
0233 &uart1 {
0234 pinctrl-names = "default";
0235 pinctrl-0 = <&pinctrl_uart1>;
0236 status = "okay";
0237 };
0238
0239 &uart2 {
0240 pinctrl-names = "default";
0241 pinctrl-0 = <&pinctrl_uart2>;
0242 status = "okay";
0243
0244 rave-sp {
0245 compatible = "zii,rave-sp-rdu2";
0246 current-speed = <1000000>;
0247 #address-cells = <1>;
0248 #size-cells = <1>;
0249
0250 watchdog {
0251 compatible = "zii,rave-sp-watchdog";
0252 };
0253
0254 eeprom@a3 {
0255 compatible = "zii,rave-sp-eeprom";
0256 reg = <0xa3 0x4000>;
0257 #address-cells = <1>;
0258 #size-cells = <1>;
0259 zii,eeprom-name = "main-eeprom";
0260 };
0261 };
0262 };
0263
0264 &uart3 {
0265 pinctrl-names = "default";
0266 pinctrl-0 = <&pinctrl_uart3>;
0267 status = "okay";
0268 };
0269
0270 &wdoga5 {
0271 status = "disabled";
0272 };
0273
0274 &iomuxc {
0275 pinctrl_dspi1: dspi1grp {
0276 fsl,pins = <
0277 VF610_PAD_PTD5__DSPI1_CS0 0x1182
0278 VF610_PAD_PTD4__DSPI1_CS1 0x1182
0279 VF610_PAD_PTC6__DSPI1_SIN 0x1181
0280 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
0281 VF610_PAD_PTC8__DSPI1_SCK 0x1182
0282 >;
0283 };
0284
0285 pinctrl_esdhc0: esdhc0grp {
0286 fsl,pins = <
0287 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
0288 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
0289 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
0290 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
0291 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
0292 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
0293 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
0294 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
0295 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
0296 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
0297 >;
0298 };
0299
0300 pinctrl_esdhc1: esdhc1grp {
0301 fsl,pins = <
0302 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
0303 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
0304 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
0305 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
0306 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
0307 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
0308 >;
0309 };
0310
0311 pinctrl_fec1: fec1grp {
0312 fsl,pins = <
0313 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
0314 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
0315 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
0316 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
0317 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
0318 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
0319 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
0320 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
0321 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
0322 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
0323 >;
0324 };
0325
0326 pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
0327 fsl,pins = <
0328 VF610_PAD_PTB28__GPIO_98 0x219d
0329 >;
0330 };
0331
0332 pinctrl_i2c0: i2c0grp {
0333 fsl,pins = <
0334 VF610_PAD_PTB14__I2C0_SCL 0x37ff
0335 VF610_PAD_PTB15__I2C0_SDA 0x37ff
0336 >;
0337 };
0338
0339 pinctrl_i2c1: i2c1grp {
0340 fsl,pins = <
0341 VF610_PAD_PTB16__I2C1_SCL 0x37ff
0342 VF610_PAD_PTB17__I2C1_SDA 0x37ff
0343 >;
0344 };
0345
0346 pinctrl_leds_debug: pinctrl-leds-debug {
0347 fsl,pins = <
0348 VF610_PAD_PTD3__GPIO_82 0x31c2
0349 >;
0350 };
0351
0352 pinctrl_uart0: uart0grp {
0353 fsl,pins = <
0354 VF610_PAD_PTB10__UART0_TX 0x21a2
0355 VF610_PAD_PTB11__UART0_RX 0x21a1
0356 >;
0357 };
0358
0359 pinctrl_uart1: uart1grp {
0360 fsl,pins = <
0361 VF610_PAD_PTB23__UART1_TX 0x21a2
0362 VF610_PAD_PTB24__UART1_RX 0x21a1
0363 >;
0364 };
0365
0366 pinctrl_uart2: uart2grp {
0367 fsl,pins = <
0368 VF610_PAD_PTD0__UART2_TX 0x21a2
0369 VF610_PAD_PTD1__UART2_RX 0x21a1
0370 >;
0371 };
0372
0373 pinctrl_uart3: uart3grp {
0374 fsl,pins = <
0375 VF610_PAD_PTA30__UART3_TX 0x21a2
0376 VF610_PAD_PTA31__UART3_RX 0x21a1
0377 >;
0378 };
0379 };
