0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 //
0003 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
0004
0005 /dts-v1/;
0006 #include "vf610.dtsi"
0007
0008 / {
0009 model = "ZII VF610 SCU4 AIB";
0010 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
0011
0012 chosen {
0013 stdout-path = &uart0;
0014 };
0015
0016 memory@80000000 {
0017 device_type = "memory";
0018 reg = <0x80000000 0x20000000>;
0019 };
0020
0021 gpio-leds {
0022 compatible = "gpio-leds";
0023 pinctrl-0 = <&pinctrl_leds_debug>;
0024 pinctrl-names = "default";
0025
0026 debug {
0027 label = "zii:green:debug1";
0028 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
0029 linux,default-trigger = "heartbeat";
0030 };
0031 };
0032
0033 mdio-mux {
0034 compatible = "mdio-mux-gpio";
0035 pinctrl-0 = <&pinctrl_mdio_mux>;
0036 pinctrl-names = "default";
0037 gpios = <&gpio4 4 GPIO_ACTIVE_HIGH
0038 &gpio4 5 GPIO_ACTIVE_HIGH
0039 &gpio3 30 GPIO_ACTIVE_HIGH
0040 &gpio3 31 GPIO_ACTIVE_HIGH>;
0041 mdio-parent-bus = <&mdio1>;
0042 #address-cells = <1>;
0043 #size-cells = <0>;
0044
0045 mdio_mux_1: mdio@1 {
0046 reg = <1>;
0047 #address-cells = <1>;
0048 #size-cells = <0>;
0049
0050 switch0: switch0@0 {
0051 compatible = "marvell,mv88e6190";
0052 reg = <0>;
0053 dsa,member = <0 0>;
0054 eeprom-length = <65536>;
0055
0056 ports {
0057 #address-cells = <1>;
0058 #size-cells = <0>;
0059
0060 port@0 {
0061 reg = <0>;
0062 label = "cpu";
0063 ethernet = <&fec1>;
0064
0065 fixed-link {
0066 speed = <100>;
0067 full-duplex;
0068 };
0069 };
0070
0071 port@1 {
0072 reg = <1>;
0073 label = "aib2main_1";
0074 };
0075
0076 port@2 {
0077 reg = <2>;
0078 label = "aib2main_2";
0079 };
0080
0081 port@3 {
0082 reg = <3>;
0083 label = "eth_cu_1000_5";
0084 };
0085
0086 port@4 {
0087 reg = <4>;
0088 label = "eth_cu_1000_6";
0089 };
0090
0091 port@5 {
0092 reg = <5>;
0093 label = "eth_cu_1000_4";
0094 };
0095
0096 port@6 {
0097 reg = <6>;
0098 label = "eth_cu_1000_7";
0099 };
0100
0101 port@7 {
0102 reg = <7>;
0103 label = "modem_pic";
0104
0105 fixed-link {
0106 speed = <100>;
0107 full-duplex;
0108 };
0109 };
0110
0111 switch0port10: port@10 {
0112 reg = <10>;
0113 label = "dsa";
0114 phy-mode = "xgmii";
0115 link = <&switch1port10
0116 &switch3port10
0117 &switch2port10>;
0118 };
0119 };
0120 };
0121 };
0122
0123 mdio_mux_2: mdio@2 {
0124 reg = <2>;
0125 #address-cells = <1>;
0126 #size-cells = <0>;
0127
0128 switch1: switch1@0 {
0129 compatible = "marvell,mv88e6190";
0130 reg = <0>;
0131 dsa,member = <0 1>;
0132 eeprom-length = <65536>;
0133
0134 ports {
0135 #address-cells = <1>;
0136 #size-cells = <0>;
0137
0138 port@1 {
0139 reg = <1>;
0140 label = "eth_cu_1000_3";
0141 };
0142
0143 port@2 {
0144 reg = <2>;
0145 label = "eth_cu_100_2";
0146 };
0147
0148 port@3 {
0149 reg = <3>;
0150 label = "eth_cu_100_3";
0151 };
0152
0153 switch1port9: port@9 {
0154 reg = <9>;
0155 label = "dsa";
0156 phy-mode = "xgmii";
0157 link = <&switch3port10
0158 &switch2port10>;
0159 };
0160
0161 switch1port10: port@10 {
0162 reg = <10>;
0163 label = "dsa";
0164 phy-mode = "xgmii";
0165 link = <&switch0port10>;
0166 };
0167 };
0168 };
0169 };
0170
0171 mdio_mux_4: mdio@4 {
0172 reg = <4>;
0173 #address-cells = <1>;
0174 #size-cells = <0>;
0175
0176 switch2: switch2@0 {
0177 compatible = "marvell,mv88e6190";
0178 reg = <0>;
0179 dsa,member = <0 2>;
0180 eeprom-length = <65536>;
0181
0182 ports {
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185
0186 port@2 {
0187 reg = <2>;
0188 label = "eth_fc_1000_2";
0189 phy-mode = "1000base-x";
0190 managed = "in-band-status";
0191 sfp = <&sff1>;
0192 };
0193
0194 port@3 {
0195 reg = <3>;
0196 label = "eth_fc_1000_3";
0197 phy-mode = "1000base-x";
0198 managed = "in-band-status";
0199 sfp = <&sff2>;
0200 };
0201
0202 port@4 {
0203 reg = <4>;
0204 label = "eth_fc_1000_4";
0205 phy-mode = "1000base-x";
0206 managed = "in-band-status";
0207 sfp = <&sff3>;
0208 };
0209
0210 port@5 {
0211 reg = <5>;
0212 label = "eth_fc_1000_5";
0213 phy-mode = "1000base-x";
0214 managed = "in-band-status";
0215 sfp = <&sff4>;
0216 };
0217
0218 port@6 {
0219 reg = <6>;
0220 label = "eth_fc_1000_6";
0221 phy-mode = "1000base-x";
0222 managed = "in-band-status";
0223 sfp = <&sff5>;
0224 };
0225
0226 port@7 {
0227 reg = <7>;
0228 label = "eth_fc_1000_7";
0229 phy-mode = "1000base-x";
0230 managed = "in-band-status";
0231 sfp = <&sff6>;
0232 };
0233
0234 port@9 {
0235 reg = <9>;
0236 label = "eth_fc_1000_1";
0237 phy-mode = "1000base-x";
0238 managed = "in-band-status";
0239 sfp = <&sff0>;
0240 };
0241
0242 switch2port10: port@10 {
0243 reg = <10>;
0244 label = "dsa";
0245 phy-mode = "2500base-x";
0246 link = <&switch3port9
0247 &switch1port9
0248 &switch0port10>;
0249 };
0250 };
0251 };
0252 };
0253
0254 mdio_mux_8: mdio@8 {
0255 reg = <8>;
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258
0259 switch3: switch3@0 {
0260 compatible = "marvell,mv88e6190";
0261 reg = <0>;
0262 dsa,member = <0 3>;
0263 eeprom-length = <65536>;
0264
0265 ports {
0266 #address-cells = <1>;
0267 #size-cells = <0>;
0268
0269 port@2 {
0270 reg = <2>;
0271 label = "eth_fc_1000_8";
0272 phy-mode = "1000base-x";
0273 managed = "in-band-status";
0274 sfp = <&sff7>;
0275 };
0276
0277 port@3 {
0278 reg = <3>;
0279 label = "eth_fc_1000_9";
0280 phy-mode = "1000base-x";
0281 managed = "in-band-status";
0282 sfp = <&sff8>;
0283 };
0284
0285 port@4 {
0286 reg = <4>;
0287 label = "eth_fc_1000_10";
0288 phy-mode = "1000base-x";
0289 managed = "in-band-status";
0290 sfp = <&sff9>;
0291 };
0292
0293 switch3port9: port@9 {
0294 reg = <9>;
0295 label = "dsa";
0296 phy-mode = "2500base-x";
0297 link = <&switch2port10>;
0298 };
0299
0300 switch3port10: port@10 {
0301 reg = <10>;
0302 label = "dsa";
0303 phy-mode = "xgmii";
0304 link = <&switch1port9
0305 &switch0port10>;
0306 };
0307 };
0308 };
0309 };
0310 };
0311
0312 sff0: sff0 {
0313 compatible = "sff,sff";
0314 i2c-bus = <&sff0_i2c>;
0315 los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
0316 tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
0317 };
0318
0319 sff1: sff1 {
0320 compatible = "sff,sff";
0321 i2c-bus = <&sff1_i2c>;
0322 los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
0323 tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
0324 };
0325
0326 sff2: sff2 {
0327 compatible = "sff,sff";
0328 i2c-bus = <&sff2_i2c>;
0329 los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
0330 tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
0331 };
0332
0333 sff3: sff3 {
0334 compatible = "sff,sff";
0335 i2c-bus = <&sff3_i2c>;
0336 los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
0337 tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
0338 };
0339
0340 sff4: sff4 {
0341 compatible = "sff,sff";
0342 i2c-bus = <&sff4_i2c>;
0343 los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
0344 tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
0345 };
0346
0347 sff5: sff5 {
0348 compatible = "sff,sff";
0349 i2c-bus = <&sff5_i2c>;
0350 los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
0351 tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>;
0352 };
0353
0354 sff6: sff6 {
0355 compatible = "sff,sff";
0356 i2c-bus = <&sff6_i2c>;
0357 los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
0358 tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
0359 };
0360
0361 sff7: sff7 {
0362 compatible = "sff,sff";
0363 i2c-bus = <&sff7_i2c>;
0364 los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>;
0365 tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
0366 };
0367
0368 sff8: sff8 {
0369 compatible = "sff,sff";
0370 i2c-bus = <&sff8_i2c>;
0371 los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>;
0372 tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
0373 };
0374
0375 sff9: sff9 {
0376 compatible = "sff,sff";
0377 i2c-bus = <&sff9_i2c>;
0378 los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>;
0379 tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
0380 };
0381
0382 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
0383 compatible = "regulator-fixed";
0384 regulator-name = "vcc_3v3_mcu";
0385 regulator-min-microvolt = <3300000>;
0386 regulator-max-microvolt = <3300000>;
0387 };
0388 };
0389
0390 &dspi0 {
0391 pinctrl-0 = <&pinctrl_dspi0>;
0392 pinctrl-names = "default";
0393 bus-num = <0>;
0394 status = "okay";
0395
0396 adc@5 {
0397 compatible = "holt,hi8435";
0398 reg = <5>;
0399 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
0400 spi-max-frequency = <1000000>;
0401 };
0402 };
0403
0404 &dspi1 {
0405 bus-num = <1>;
0406 pinctrl-names = "default";
0407 pinctrl-0 = <&pinctrl_dspi1>;
0408 status = "okay";
0409
0410 flash@0 {
0411 #address-cells = <1>;
0412 #size-cells = <1>;
0413 compatible = "jedec,spi-nor";
0414 reg = <0>;
0415 spi-max-frequency = <50000000>;
0416
0417 partition@0 {
0418 label = "m25p128-0";
0419 reg = <0x0 0x01000000>;
0420 };
0421 };
0422
0423 flash@1 {
0424 #address-cells = <1>;
0425 #size-cells = <1>;
0426 compatible = "jedec,spi-nor";
0427 reg = <1>;
0428 spi-max-frequency = <50000000>;
0429
0430 partition@0 {
0431 label = "m25p128-1";
0432 reg = <0x0 0x01000000>;
0433 };
0434 };
0435 };
0436
0437 &adc0 {
0438 vref-supply = <®_vcc_3v3_mcu>;
0439 status = "okay";
0440 };
0441
0442 &adc1 {
0443 vref-supply = <®_vcc_3v3_mcu>;
0444 status = "okay";
0445 };
0446
0447 &edma0 {
0448 status = "okay";
0449 };
0450
0451 &edma1 {
0452 status = "okay";
0453 };
0454
0455 &esdhc0 {
0456 pinctrl-names = "default";
0457 pinctrl-0 = <&pinctrl_esdhc0>;
0458 bus-width = <8>;
0459 non-removable;
0460 no-1-8-v;
0461 no-sd;
0462 no-sdio;
0463 keep-power-in-suspend;
0464 status = "okay";
0465 };
0466
0467 &esdhc1 {
0468 pinctrl-names = "default";
0469 pinctrl-0 = <&pinctrl_esdhc1>;
0470 bus-width = <4>;
0471 no-sdio;
0472 status = "okay";
0473 };
0474
0475 &fec1 {
0476 phy-mode = "rmii";
0477 pinctrl-names = "default";
0478 pinctrl-0 = <&pinctrl_fec1>;
0479 status = "okay";
0480
0481 fixed-link {
0482 speed = <100>;
0483 full-duplex;
0484 };
0485
0486 mdio1: mdio {
0487 #address-cells = <1>;
0488 #size-cells = <0>;
0489 };
0490 };
0491
0492 &i2c0 {
0493 clock-frequency = <100000>;
0494 pinctrl-names = "default";
0495 pinctrl-0 = <&pinctrl_i2c0>;
0496 status = "okay";
0497
0498 gpio5: io-expander@20 {
0499 compatible = "nxp,pca9554";
0500 reg = <0x20>;
0501 gpio-controller;
0502 #gpio-cells = <2>;
0503 };
0504
0505 gpio6: io-expander@22 {
0506 compatible = "nxp,pca9554";
0507 reg = <0x22>;
0508 gpio-controller;
0509 #gpio-cells = <2>;
0510 };
0511
0512 temp-sensor@48 {
0513 compatible = "national,lm75";
0514 reg = <0x48>;
0515 };
0516
0517 eeprom@50 {
0518 compatible = "atmel,24c04";
0519 reg = <0x50>;
0520 };
0521
0522 eeprom@52 {
0523 compatible = "atmel,24c04";
0524 reg = <0x52>;
0525 };
0526
0527 elapsed-time-recorder@6b {
0528 compatible = "dallas,ds1682";
0529 reg = <0x6b>;
0530 };
0531 };
0532
0533 &i2c1 {
0534 clock-frequency = <100000>;
0535 pinctrl-names = "default";
0536 pinctrl-0 = <&pinctrl_i2c1>;
0537 status = "okay";
0538
0539 watchdog@38 {
0540 compatible = "zii,rave-wdt";
0541 reg = <0x38>;
0542 };
0543
0544 adc@4a {
0545 compatible = "adi,adt7411";
0546 reg = <0x4a>;
0547 };
0548 };
0549
0550 &i2c2 {
0551 clock-frequency = <100000>;
0552 pinctrl-names = "default";
0553 pinctrl-0 = <&pinctrl_i2c2>;
0554 status = "okay";
0555
0556 gpio9: io-expander@20 {
0557 compatible = "semtech,sx1503q";
0558 pinctrl-names = "default";
0559 pinctrl-0 = <&pinctrl_sx1503_20>;
0560 #gpio-cells = <2>;
0561 reg = <0x20>;
0562 gpio-controller;
0563 interrupt-parent = <&gpio1>;
0564 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
0565 };
0566
0567 temp-sensor@4e {
0568 compatible = "national,lm75";
0569 reg = <0x4e>;
0570 };
0571
0572 temp-sensor@4f {
0573 compatible = "national,lm75";
0574 reg = <0x4f>;
0575 };
0576
0577 gpio7: io-expander@23 {
0578 compatible = "nxp,pca9555";
0579 gpio-controller;
0580 #gpio-cells = <2>;
0581 reg = <0x23>;
0582 };
0583
0584 adc@4a {
0585 compatible = "adi,adt7411";
0586 reg = <0x4a>;
0587 };
0588
0589 eeprom@54 {
0590 compatible = "atmel,24c08";
0591 reg = <0x54>;
0592 };
0593
0594 i2c-mux@70 {
0595 compatible = "nxp,pca9548";
0596 pinctrl-names = "default";
0597 #address-cells = <1>;
0598 #size-cells = <0>;
0599 reg = <0x70>;
0600 i2c-mux-idle-disconnect;
0601
0602 sff0_i2c: i2c@1 {
0603 #address-cells = <1>;
0604 #size-cells = <0>;
0605 reg = <1>;
0606 };
0607
0608 sff1_i2c: i2c@2 {
0609 #address-cells = <1>;
0610 #size-cells = <0>;
0611 reg = <2>;
0612 };
0613
0614 sff2_i2c: i2c@3 {
0615 #address-cells = <1>;
0616 #size-cells = <0>;
0617 reg = <3>;
0618 };
0619
0620 sff3_i2c: i2c@4 {
0621 #address-cells = <1>;
0622 #size-cells = <0>;
0623 reg = <4>;
0624 };
0625
0626 sff4_i2c: i2c@5 {
0627 #address-cells = <1>;
0628 #size-cells = <0>;
0629 reg = <5>;
0630 };
0631 };
0632
0633 i2c-mux@71 {
0634 compatible = "nxp,pca9548";
0635 pinctrl-names = "default";
0636 reg = <0x71>;
0637 #address-cells = <1>;
0638 #size-cells = <0>;
0639 i2c-mux-idle-disconnect;
0640
0641 sff5_i2c: i2c@1 {
0642 #address-cells = <1>;
0643 #size-cells = <0>;
0644 reg = <1>;
0645 };
0646
0647 sff6_i2c: i2c@2 {
0648 #address-cells = <1>;
0649 #size-cells = <0>;
0650 reg = <2>;
0651 };
0652
0653 sff7_i2c: i2c@3 {
0654 #address-cells = <1>;
0655 #size-cells = <0>;
0656 reg = <3>;
0657 };
0658
0659 sff8_i2c: i2c@4 {
0660 #address-cells = <1>;
0661 #size-cells = <0>;
0662 reg = <4>;
0663 };
0664
0665 sff9_i2c: i2c@5 {
0666 #address-cells = <1>;
0667 #size-cells = <0>;
0668 reg = <5>;
0669 };
0670 };
0671 };
0672
0673 &snvsrtc {
0674 status = "disabled";
0675 };
0676
0677 &uart0 {
0678 pinctrl-names = "default";
0679 pinctrl-0 = <&pinctrl_uart0>;
0680 status = "okay";
0681 };
0682
0683 &uart1 {
0684 linux,rs485-enabled-at-boot-time;
0685 pinctrl-names = "default";
0686 pinctrl-0 = <&pinctrl_uart1>;
0687 status = "okay";
0688 };
0689
0690 &uart2 {
0691 linux,rs485-enabled-at-boot-time;
0692 pinctrl-names = "default";
0693 pinctrl-0 = <&pinctrl_uart2>;
0694 status = "okay";
0695 };
0696
0697 &iomuxc {
0698 pinctrl_dspi0: dspi0grp {
0699 fsl,pins = <
0700 VF610_PAD_PTB19__DSPI0_CS0 0x1182
0701 VF610_PAD_PTB18__DSPI0_CS1 0x1182
0702 VF610_PAD_PTB13__DSPI0_CS4 0x1182
0703 VF610_PAD_PTB12__DSPI0_CS5 0x1182
0704 VF610_PAD_PTB20__DSPI0_SIN 0x1181
0705 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
0706 VF610_PAD_PTB22__DSPI0_SCK 0x1182
0707 >;
0708 };
0709
0710 pinctrl_dspi1: dspi1grp {
0711 fsl,pins = <
0712 VF610_PAD_PTD5__DSPI1_CS0 0x1182
0713 VF610_PAD_PTD4__DSPI1_CS1 0x1182
0714 VF610_PAD_PTC6__DSPI1_SIN 0x1181
0715 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
0716 VF610_PAD_PTC8__DSPI1_SCK 0x1182
0717 >;
0718 };
0719
0720 pinctrl_dspi2: dspi2gpio {
0721 fsl,pins = <
0722 VF610_PAD_PTD30__GPIO_64 0x33e2
0723 VF610_PAD_PTD29__GPIO_65 0x33e1
0724 VF610_PAD_PTD28__GPIO_66 0x33e2
0725 VF610_PAD_PTD27__GPIO_67 0x33e2
0726 VF610_PAD_PTD26__GPIO_68 0x31c2
0727 >;
0728 };
0729
0730 pinctrl_esdhc0: esdhc0grp {
0731 fsl,pins = <
0732 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
0733 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
0734 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
0735 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
0736 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
0737 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
0738 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
0739 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
0740 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
0741 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
0742 >;
0743 };
0744
0745 pinctrl_esdhc1: esdhc1grp {
0746 fsl,pins = <
0747 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
0748 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
0749 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
0750 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
0751 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
0752 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
0753 >;
0754 };
0755
0756 pinctrl_fec1: fec1grp {
0757 fsl,pins = <
0758 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
0759 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
0760 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
0761 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
0762 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
0763 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
0764 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
0765 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
0766 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
0767 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
0768 >;
0769 };
0770
0771 pinctrl_i2c0: i2c0grp {
0772 fsl,pins = <
0773 VF610_PAD_PTB14__I2C0_SCL 0x37ff
0774 VF610_PAD_PTB15__I2C0_SDA 0x37ff
0775 >;
0776 };
0777
0778 pinctrl_i2c1: i2c1grp {
0779 fsl,pins = <
0780 VF610_PAD_PTB16__I2C1_SCL 0x37ff
0781 VF610_PAD_PTB17__I2C1_SDA 0x37ff
0782 >;
0783 };
0784
0785 pinctrl_i2c2: i2c2grp {
0786 fsl,pins = <
0787 VF610_PAD_PTA22__I2C2_SCL 0x37ff
0788 VF610_PAD_PTA23__I2C2_SDA 0x37ff
0789 >;
0790 };
0791
0792 pinctrl_leds_debug: pinctrl-leds-debug {
0793 fsl,pins = <
0794 VF610_PAD_PTB26__GPIO_96 0x31c2
0795 >;
0796 };
0797
0798 pinctrl_mdio_mux: pinctrl-mdio-mux {
0799 fsl,pins = <
0800 VF610_PAD_PTE27__GPIO_132 0x31c2
0801 VF610_PAD_PTE28__GPIO_133 0x31c2
0802 VF610_PAD_PTE21__GPIO_126 0x31c2
0803 VF610_PAD_PTE22__GPIO_127 0x31c2
0804 >;
0805 };
0806
0807 pinctrl_qspi0: qspi0grp {
0808 fsl,pins = <
0809 VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
0810 VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
0811 VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
0812 VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
0813 VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
0814 VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
0815 >;
0816 };
0817
0818 pinctrl_sx1503_20: pinctrl-sx1503-20 {
0819 fsl,pins = <
0820 VF610_PAD_PTD31__GPIO_63 0x219d
0821 >;
0822 };
0823
0824 pinctrl_uart0: uart0grp {
0825 fsl,pins = <
0826 VF610_PAD_PTB10__UART0_TX 0x21a2
0827 VF610_PAD_PTB11__UART0_RX 0x21a1
0828 >;
0829 };
0830
0831 pinctrl_uart1: uart1grp {
0832 fsl,pins = <
0833 VF610_PAD_PTB23__UART1_TX 0x21a2
0834 VF610_PAD_PTB24__UART1_RX 0x21a1
0835 VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
0836 >;
0837 };
0838
0839 pinctrl_uart2: uart2grp {
0840 fsl,pins = <
0841 VF610_PAD_PTD0__UART2_TX 0x21a2
0842 VF610_PAD_PTD1__UART2_RX 0x21a1
0843 VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
0844 >;
0845 };
0846 };
