OSCL-LXR |
|
|
|
|||
0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
0004 */
0005
0006 /dts-v1/;
0007 #include "vf610-zii-dev.dtsi"
0008
0009 / {
0010 model = "ZII VF610 Development Board, Rev C";
0011 compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
0012
0013 mdio-mux {
0014 compatible = "mdio-mux-gpio";
0015 pinctrl-0 = <&pinctrl_mdio_mux>;
0016 pinctrl-names = "default";
0017 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
0018 &gpio0 9 GPIO_ACTIVE_HIGH
0019 &gpio0 25 GPIO_ACTIVE_HIGH>;
0020 mdio-parent-bus = <&mdio1>;
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023
0024 mdio_mux_1: mdio@1 {
0025 reg = <1>;
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028
0029 switch0: switch@0 {
0030 compatible = "marvell,mv88e6190";
0031 pinctrl-0 = <&pinctrl_gpio_switch0>;
0032 pinctrl-names = "default";
0033 reg = <0>;
0034 dsa,member = <0 0>;
0035 eeprom-length = <65536>;
0036 interrupt-parent = <&gpio0>;
0037 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
0038 interrupt-controller;
0039 #interrupt-cells = <2>;
0040
0041 ports {
0042 #address-cells = <1>;
0043 #size-cells = <0>;
0044
0045 port@0 {
0046 reg = <0>;
0047 label = "cpu";
0048 ethernet = <&fec1>;
0049
0050 fixed-link {
0051 speed = <100>;
0052 full-duplex;
0053 };
0054 };
0055
0056 port@1 {
0057 reg = <1>;
0058 label = "lan1";
0059 phy-handle = <&switch0phy1>;
0060 };
0061
0062 port@2 {
0063 reg = <2>;
0064 label = "lan2";
0065 phy-handle = <&switch0phy2>;
0066 };
0067
0068 port@3 {
0069 reg = <3>;
0070 label = "lan3";
0071 phy-handle = <&switch0phy3>;
0072 };
0073
0074 port@4 {
0075 reg = <4>;
0076 label = "lan4";
0077 phy-handle = <&switch0phy4>;
0078 };
0079
0080 switch0port10: port@10 {
0081 reg = <10>;
0082 label = "dsa";
0083 phy-mode = "xaui";
0084 link = <&switch1port10>;
0085 };
0086 };
0087
0088 mdio {
0089 #address-cells = <1>;
0090 #size-cells = <0>;
0091
0092 switch0phy1: switch0phy@1 {
0093 reg = <1>;
0094 interrupt-parent = <&switch0>;
0095 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
0096 };
0097
0098 switch0phy2: switch0phy@2 {
0099 reg = <2>;
0100 interrupt-parent = <&switch0>;
0101 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
0102 };
0103
0104 switch0phy3: switch0phy@3 {
0105 reg = <3>;
0106 interrupt-parent = <&switch0>;
0107 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
0108 };
0109
0110 switch0phy4: switch0phy@4 {
0111 reg = <4>;
0112 interrupt-parent = <&switch0>;
0113 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0114 };
0115 };
0116 };
0117 };
0118
0119 mdio_mux_2: mdio@2 {
0120 reg = <2>;
0121 #address-cells = <1>;
0122 #size-cells = <0>;
0123
0124 switch1: switch@0 {
0125 compatible = "marvell,mv88e6190";
0126 pinctrl-0 = <&pinctrl_gpio_switch1>;
0127 pinctrl-names = "default";
0128 reg = <0>;
0129 dsa,member = <0 1>;
0130 eeprom-length = <65536>;
0131 interrupt-parent = <&gpio0>;
0132 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
0133 interrupt-controller;
0134 #interrupt-cells = <2>;
0135
0136 ports {
0137 #address-cells = <1>;
0138 #size-cells = <0>;
0139
0140 port@1 {
0141 reg = <1>;
0142 label = "lan5";
0143 phy-handle = <&switch1phy1>;
0144 };
0145
0146 port@2 {
0147 reg = <2>;
0148 label = "lan6";
0149 phy-handle = <&switch1phy2>;
0150 };
0151
0152 port@3 {
0153 reg = <3>;
0154 label = "lan7";
0155 phy-handle = <&switch1phy3>;
0156 };
0157
0158 port@4 {
0159 reg = <4>;
0160 label = "lan8";
0161 phy-handle = <&switch1phy4>;
0162 };
0163
0164 port@9 {
0165 reg = <9>;
0166 label = "sff2";
0167 phy-mode = "1000base-x";
0168 managed = "in-band-status";
0169 sfp = <&sff2>;
0170 };
0171
0172 switch1port10: port@10 {
0173 reg = <10>;
0174 label = "dsa";
0175 phy-mode = "xaui";
0176 link = <&switch0port10>;
0177 };
0178 };
0179 mdio {
0180 #address-cells = <1>;
0181 #size-cells = <0>;
0182
0183 switch1phy1: switch1phy@1 {
0184 reg = <1>;
0185 interrupt-parent = <&switch1>;
0186 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
0187 };
0188
0189 switch1phy2: switch1phy@2 {
0190 reg = <2>;
0191 interrupt-parent = <&switch1>;
0192 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
0193 };
0194
0195 switch1phy3: switch1phy@3 {
0196 reg = <3>;
0197 interrupt-parent = <&switch1>;
0198 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
0199 };
0200
0201 switch1phy4: switch1phy@4 {
0202 reg = <4>;
0203 interrupt-parent = <&switch1>;
0204 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0205 };
0206 };
0207 };
0208 };
0209
0210 mdio_mux_4: mdio@4 {
0211 reg = <4>;
0212 #address-cells = <1>;
0213 #size-cells = <0>;
0214 };
0215 };
0216
0217 sff2: sff2 {
0218 /* lower */
0219 compatible = "sff,sff";
0220 i2c-bus = <&sff2_i2c>;
0221 los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
0222 tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
0223 };
0224
0225 sff3: sff3 {
0226 /* upper */
0227 compatible = "sff,sff";
0228 i2c-bus = <&sff3_i2c>;
0229 los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
0230 tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
0231 };
0232 };
0233
0234 &dspi0 {
0235 bus-num = <0>;
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_dspi0>;
0238 status = "okay";
0239 spi-num-chipselects = <2>;
0240
0241 flash@0 {
0242 compatible = "m25p128", "jedec,spi-nor";
0243 #address-cells = <1>;
0244 #size-cells = <1>;
0245 reg = <0>;
0246 spi-max-frequency = <1000000>;
0247 };
0248
0249 atzb-rf-233@1 {
0250 compatible = "atmel,at86rf233";
0251
0252 pinctrl-names = "default";
0253 pinctrl-0 = <&pinctr_atzb_rf_233>;
0254
0255 spi-max-frequency = <7500000>;
0256 reg = <1>;
0257 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0258 interrupt-parent = <&gpio3>;
0259 xtal-trim = /bits/ 8 <0x06>;
0260
0261 sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
0262 reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
0263
0264 fsl,spi-cs-sck-delay = <180>;
0265 fsl,spi-sck-cs-delay = <250>;
0266 };
0267 };
0268
0269 &i2c0 {
0270 /*
0271 * U712
0272 *
0273 * Exposed signals:
0274 * P1 - WE2_CMD
0275 * P2 - WE2_CLK
0276 */
0277 gpio5: io-expander@18 {
0278 compatible = "nxp,pca9557";
0279 reg = <0x18>;
0280 gpio-controller;
0281 #gpio-cells = <2>;
0282 };
0283
0284 /*
0285 * U121
0286 *
0287 * Exposed signals:
0288 * I/O0 - ENET_SWR_EN
0289 * I/O1 - ESW1_RESETn
0290 * I/O2 - ARINC_RESET
0291 * I/O3 - DD1_IO_RESET
0292 * I/O4 - ESW2_RESETn
0293 * I/O5 - ESW3_RESETn
0294 * I/O6 - ESW4_RESETn
0295 * I/O8 - TP909
0296 * I/O9 - FEM_SEL
0297 * I/O10 - WIFI_RESETn
0298 * I/O11 - PHY_RSTn
0299 * I/O12 - OPT1_SD
0300 * I/O13 - OPT2_SD
0301 * I/O14 - OPT1_TX_DIS
0302 * I/O15 - OPT2_TX_DIS
0303 */
0304 gpio6: sx1503@20 {
0305 compatible = "semtech,sx1503q";
0306
0307 pinctrl-names = "default";
0308 pinctrl-0 = <&pinctrl_sx1503_20>;
0309 #gpio-cells = <2>;
0310 #interrupt-cells = <2>;
0311 reg = <0x20>;
0312 interrupt-parent = <&gpio0>;
0313 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
0314 gpio-controller;
0315 interrupt-controller;
0316 };
0317
0318 /*
0319 * U715
0320 *
0321 * Exposed signals:
0322 * IO0 - WE1_CLK
0323 * IO1 - WE1_CMD
0324 */
0325 gpio7: io-expander@22 {
0326 compatible = "nxp,pca9554";
0327 reg = <0x22>;
0328 gpio-controller;
0329 #gpio-cells = <2>;
0330
0331 };
0332 };
0333
0334 &i2c1 {
0335 eeprom@50 {
0336 compatible = "atmel,24c02";
0337 reg = <0x50>;
0338 read-only;
0339 };
0340 };
0341
0342 &i2c2 {
0343 tca9548@70 {
0344 compatible = "nxp,pca9548";
0345 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
0346 pinctrl-names = "default";
0347 #address-cells = <1>;
0348 #size-cells = <0>;
0349 reg = <0x70>;
0350 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
0351
0352 i2c@0 {
0353 #address-cells = <1>;
0354 #size-cells = <0>;
0355 reg = <0>;
0356 };
0357
0358 sff2_i2c: i2c@1 {
0359 #address-cells = <1>;
0360 #size-cells = <0>;
0361 reg = <1>;
0362 };
0363
0364 sff3_i2c: i2c@2 {
0365 #address-cells = <1>;
0366 #size-cells = <0>;
0367 reg = <2>;
0368 };
0369
0370 i2c@3 {
0371 #address-cells = <1>;
0372 #size-cells = <0>;
0373 reg = <3>;
0374 };
0375 };
0376 };
0377
0378 &uart3 {
0379 pinctrl-names = "default";
0380 pinctrl-0 = <&pinctrl_uart3>;
0381 status = "okay";
0382 };
0383
0384 &gpio0 {
0385 eth0_intrp {
0386 gpio-hog;
0387 gpios = <23 GPIO_ACTIVE_HIGH>;
0388 input;
0389 line-name = "sx1503-irq";
0390 };
0391 };
0392
0393 &gpio3 {
0394 eth0_intrp {
0395 gpio-hog;
0396 gpios = <2 GPIO_ACTIVE_HIGH>;
0397 input;
0398 line-name = "eth0-intrp";
0399 };
0400 };
0401
0402 &fec0 {
0403 mdio {
0404 #address-cells = <1>;
0405 #size-cells = <0>;
0406 status = "okay";
0407
0408 ethernet-phy@0 {
0409 compatible = "ethernet-phy-ieee802.3-c22";
0410
0411 pinctrl-names = "default";
0412 pinctrl-0 = <&pinctrl_fec0_phy_int>;
0413
0414 interrupt-parent = <&gpio3>;
0415 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0416 reg = <0>;
0417 };
0418 };
0419 };
0420
0421 &iomuxc {
0422 pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
0423 fsl,pins = <
0424 VF610_PAD_PTB2__GPIO_24 0x31c2
0425 VF610_PAD_PTE27__GPIO_132 0x33e2
0426 >;
0427 };
0428
0429
0430 pinctrl_sx1503_20: pinctrl-sx1503-20 {
0431 fsl,pins = <
0432 VF610_PAD_PTB1__GPIO_23 0x219d
0433 >;
0434 };
0435
0436 pinctrl_uart3: uart3grp {
0437 fsl,pins = <
0438 VF610_PAD_PTA20__UART3_TX 0x21a2
0439 VF610_PAD_PTA21__UART3_RX 0x21a1
0440 >;
0441 };
0442
0443 pinctrl_mdio_mux: pinctrl-mdio-mux {
0444 fsl,pins = <
0445 VF610_PAD_PTA18__GPIO_8 0x31c2
0446 VF610_PAD_PTA19__GPIO_9 0x31c2
0447 VF610_PAD_PTB3__GPIO_25 0x31c2
0448 >;
0449 };
0450
0451 pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {
0452 fsl,pins = <
0453 VF610_PAD_PTB28__GPIO_98 0x219d
0454 >;
0455 };
0456 };
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|