0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002
0003 /*
0004 * Copyright (C) 2018 Zodiac Inflight Innovations
0005 */
0006
0007 /dts-v1/;
0008 #include "vf610.dtsi"
0009
0010 / {
0011 model = "ZII VF610 CFU1 Board";
0012 compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610";
0013
0014 chosen {
0015 stdout-path = &uart0;
0016 };
0017
0018 memory@80000000 {
0019 device_type = "memory";
0020 reg = <0x80000000 0x20000000>;
0021 };
0022
0023 gpio-leds {
0024 compatible = "gpio-leds";
0025 pinctrl-0 = <&pinctrl_leds_debug>;
0026 pinctrl-names = "default";
0027
0028 led-debug {
0029 label = "zii:green:debug1";
0030 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
0031 linux,default-trigger = "heartbeat";
0032 };
0033
0034 led-fail {
0035 label = "zii:red:fail";
0036 gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
0037 default-state = "off";
0038 };
0039
0040 led-status {
0041 label = "zii:green:status";
0042 gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
0043 default-state = "off";
0044 };
0045
0046 led-debug-a {
0047 label = "zii:green:debug_a";
0048 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
0049 default-state = "off";
0050 };
0051
0052 led-debug-b {
0053 label = "zii:green:debug_b";
0054 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
0055 default-state = "off";
0056 };
0057 };
0058
0059 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
0060 compatible = "regulator-fixed";
0061 regulator-name = "vcc_3v3_mcu";
0062 regulator-min-microvolt = <3300000>;
0063 regulator-max-microvolt = <3300000>;
0064 };
0065
0066 sff: sfp {
0067 compatible = "sff,sff";
0068 pinctrl-0 = <&pinctrl_optical>;
0069 pinctrl-names = "default";
0070 i2c-bus = <&i2c0>;
0071 los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
0072 tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
0073 };
0074
0075 supply-voltage-monitor {
0076 compatible = "iio-hwmon";
0077 io-channels = <&adc0 8>, /* 28VDC_IN */
0078 <&adc0 9>, /* +3.3V */
0079 <&adc1 8>, /* VCC_1V5 */
0080 <&adc1 9>; /* VCC_1V2 */
0081 };
0082 };
0083
0084 &adc0 {
0085 vref-supply = <®_vcc_3v3_mcu>;
0086 status = "okay";
0087 };
0088
0089 &adc1 {
0090 vref-supply = <®_vcc_3v3_mcu>;
0091 status = "okay";
0092 };
0093
0094 &dspi1 {
0095 bus-num = <1>;
0096 pinctrl-names = "default";
0097 pinctrl-0 = <&pinctrl_dspi1>;
0098 /*
0099 * Some CFU1s come with SPI-NOR chip DNPed, so we leave this
0100 * node disabled by default and rely on bootloader to enable
0101 * it when appropriate.
0102 */
0103 status = "disabled";
0104
0105 flash@0 {
0106 #address-cells = <1>;
0107 #size-cells = <1>;
0108 compatible = "m25p128", "jedec,spi-nor";
0109 reg = <0>;
0110 spi-max-frequency = <50000000>;
0111
0112 partition@0 {
0113 label = "m25p128-0";
0114 reg = <0x0 0x01000000>;
0115 };
0116 };
0117 };
0118
0119 &edma0 {
0120 status = "okay";
0121 };
0122
0123 &edma1 {
0124 status = "okay";
0125 };
0126
0127 &esdhc0 {
0128 pinctrl-names = "default";
0129 pinctrl-0 = <&pinctrl_esdhc0>;
0130 bus-width = <8>;
0131 non-removable;
0132 no-1-8-v;
0133 keep-power-in-suspend;
0134 no-sdio;
0135 no-sd;
0136 status = "okay";
0137 };
0138
0139 &esdhc1 {
0140 pinctrl-names = "default";
0141 pinctrl-0 = <&pinctrl_esdhc1>;
0142 bus-width = <4>;
0143 no-sdio;
0144 status = "okay";
0145 };
0146
0147 &fec1 {
0148 phy-mode = "rmii";
0149 pinctrl-names = "default";
0150 pinctrl-0 = <&pinctrl_fec1>;
0151 status = "okay";
0152
0153 fixed-link {
0154 speed = <100>;
0155 full-duplex;
0156 };
0157
0158 mdio1: mdio {
0159 #address-cells = <1>;
0160 #size-cells = <0>;
0161 clock-frequency = <12500000>;
0162 suppress-preamble;
0163 status = "okay";
0164
0165 switch0: switch0@0 {
0166 compatible = "marvell,mv88e6085";
0167 pinctrl-names = "default";
0168 pinctrl-0 = <&pinctrl_switch>;
0169 reg = <0>;
0170 eeprom-length = <512>;
0171 interrupt-parent = <&gpio3>;
0172 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0173 interrupt-controller;
0174 #interrupt-cells = <2>;
0175
0176 ports {
0177 #address-cells = <1>;
0178 #size-cells = <0>;
0179
0180 port@0 {
0181 reg = <0>;
0182 label = "eth_cu_1000_1";
0183 };
0184
0185 port@1 {
0186 reg = <1>;
0187 label = "eth_cu_1000_2";
0188 };
0189
0190 port@2 {
0191 reg = <2>;
0192 label = "eth_cu_1000_3";
0193 };
0194
0195 port@5 {
0196 reg = <5>;
0197 label = "eth_fc_1000_1";
0198 phy-mode = "1000base-x";
0199 managed = "in-band-status";
0200 sfp = <&sff>;
0201 };
0202
0203 port@6 {
0204 reg = <6>;
0205 label = "cpu";
0206 ethernet = <&fec1>;
0207
0208 fixed-link {
0209 speed = <100>;
0210 full-duplex;
0211 };
0212 };
0213 };
0214 };
0215 };
0216 };
0217
0218 &i2c0 {
0219 clock-frequency = <100000>;
0220 pinctrl-names = "default";
0221 pinctrl-0 = <&pinctrl_i2c0>;
0222 status = "okay";
0223
0224 io-expander@22 {
0225 compatible = "nxp,pca9554";
0226 reg = <0x22>;
0227 gpio-controller;
0228 #gpio-cells = <2>;
0229 };
0230
0231 lm75@48 {
0232 compatible = "national,lm75";
0233 reg = <0x48>;
0234 };
0235
0236 eeprom@52 {
0237 compatible = "atmel,24c04";
0238 reg = <0x52>;
0239 label = "nvm";
0240 };
0241
0242 eeprom@54 {
0243 compatible = "atmel,24c04";
0244 reg = <0x54>;
0245 label = "nameplate";
0246 };
0247 };
0248
0249 &i2c1 {
0250 clock-frequency = <100000>;
0251 pinctrl-names = "default";
0252 pinctrl-0 = <&pinctrl_i2c1>;
0253 status = "okay";
0254
0255 watchdog@38 {
0256 compatible = "zii,rave-wdt";
0257 reg = <0x38>;
0258 };
0259 };
0260
0261 &snvsrtc {
0262 status = "disabled";
0263 };
0264
0265 &uart0 {
0266 pinctrl-names = "default";
0267 pinctrl-0 = <&pinctrl_uart0>;
0268 status = "okay";
0269 };
0270
0271 &iomuxc {
0272 pinctrl_dspi1: dspi1grp {
0273 fsl,pins = <
0274 VF610_PAD_PTD5__DSPI1_CS0 0x1182
0275 VF610_PAD_PTC6__DSPI1_SIN 0x1181
0276 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
0277 VF610_PAD_PTC8__DSPI1_SCK 0x1182
0278 >;
0279 };
0280
0281 pinctrl_esdhc0: esdhc0grp {
0282 fsl,pins = <
0283 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
0284 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
0285 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
0286 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
0287 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
0288 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
0289 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
0290 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
0291 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
0292 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
0293 >;
0294 };
0295
0296 pinctrl_esdhc1: esdhc1grp {
0297 fsl,pins = <
0298 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
0299 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
0300 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
0301 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
0302 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
0303 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
0304 >;
0305 };
0306
0307 pinctrl_fec1: fec1grp {
0308 fsl,pins = <
0309 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
0310 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe
0311 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
0312 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
0313 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
0314 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
0315 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
0316 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
0317 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
0318 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
0319 >;
0320 };
0321
0322 pinctrl_i2c0: i2c0grp {
0323 fsl,pins = <
0324 VF610_PAD_PTB14__I2C0_SCL 0x37ff
0325 VF610_PAD_PTB15__I2C0_SDA 0x37ff
0326 >;
0327 };
0328
0329 pinctrl_i2c1: i2c1grp {
0330 fsl,pins = <
0331 VF610_PAD_PTB16__I2C1_SCL 0x37ff
0332 VF610_PAD_PTB17__I2C1_SDA 0x37ff
0333 >;
0334 };
0335
0336 pinctrl_leds_debug: pinctrl-leds-debug {
0337 fsl,pins = <
0338 VF610_PAD_PTD3__GPIO_82 0x31c2
0339 VF610_PAD_PTE3__GPIO_108 0x31c2
0340 VF610_PAD_PTE4__GPIO_109 0x31c2
0341 VF610_PAD_PTE5__GPIO_110 0x31c2
0342 VF610_PAD_PTE6__GPIO_111 0x31c2
0343 >;
0344 };
0345
0346 pinctrl_optical: optical-grp {
0347 fsl,pins = <
0348 /* SFF SD input */
0349 VF610_PAD_PTE27__GPIO_132 0x3061
0350
0351 /* SFF Transmit disable output */
0352 VF610_PAD_PTE13__GPIO_118 0x3043
0353 >;
0354 };
0355
0356 pinctrl_switch: switch-grp {
0357 fsl,pins = <
0358 VF610_PAD_PTB28__GPIO_98 0x3061
0359 >;
0360 };
0361
0362 pinctrl_uart0: uart0grp {
0363 fsl,pins = <
0364 VF610_PAD_PTB10__UART0_TX 0x21a2
0365 VF610_PAD_PTB11__UART0_RX 0x21a1
0366 >;
0367 };
0368 };
