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OSCL-LXR

 
 

    


0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2013 Freescale Semiconductor, Inc.
0004  * Copyright 2013 Linaro Limited
0005  */
0006 
0007 /dts-v1/;
0008 #include "vf610.dtsi"
0009 
0010 / {
0011         model = "PHYTEC Cosmic/Cosmic+ Board";
0012         compatible = "phytec,vf610-cosmic", "fsl,vf610";
0013 
0014         chosen {
0015                 bootargs = "console=ttyLP1,115200";
0016         };
0017 
0018         memory@80000000 {
0019                 device_type = "memory";
0020                 reg = <0x80000000 0x10000000>;
0021         };
0022 
0023         enet_ext: enet_ext {
0024                 compatible = "fixed-clock";
0025                 #clock-cells = <0>;
0026                 clock-frequency = <50000000>;
0027         };
0028 };
0029 
0030 &clks {
0031         clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
0032         clock-names = "sxosc", "fxosc", "enet_ext";
0033 };
0034 
0035 &esdhc1 {
0036         pinctrl-names = "default";
0037         pinctrl-0 = <&pinctrl_esdhc1>;
0038         bus-width = <4>;
0039         status = "okay";
0040 };
0041 
0042 &fec1 {
0043         phy-mode = "rmii";
0044         pinctrl-names = "default";
0045         pinctrl-0 = <&pinctrl_fec1>;
0046         status = "okay";
0047 };
0048 
0049 &iomuxc {
0050         vf610-cosmic {
0051                 pinctrl_esdhc1: esdhc1grp {
0052                         fsl,pins = <
0053                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
0054                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
0055                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
0056                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
0057                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
0058                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
0059                                 VF610_PAD_PTB28__GPIO_98        0x219d
0060                         >;
0061                 };
0062 
0063                 pinctrl_fec1: fec1grp {
0064                         fsl,pins = <
0065                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
0066                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
0067                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
0068                                 VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
0069                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
0070                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
0071                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
0072                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
0073                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
0074                         >;
0075                 };
0076 
0077                 pinctrl_uart1: uart1grp {
0078                         fsl,pins = <
0079                                 VF610_PAD_PTB4__UART1_TX                0x21a2
0080                                 VF610_PAD_PTB5__UART1_RX                0x21a1
0081                         >;
0082                 };
0083         };
0084 };
0085 
0086 &uart1 {
0087         pinctrl-names = "default";
0088         pinctrl-0 = <&pinctrl_uart1>;
0089         status = "okay";
0090 };