0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2018
0004 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
0005 */
0006
0007 /dts-v1/;
0008 #include "vf610.dtsi"
0009
0010 / {
0011 model = "Liebherr BK4 controller";
0012 compatible = "lwn,bk4", "fsl,vf610";
0013
0014 chosen {
0015 stdout-path = &uart1;
0016 };
0017
0018 memory@80000000 {
0019 device_type = "memory";
0020 reg = <0x80000000 0x8000000>;
0021 };
0022
0023 audio_ext: oscillator-audio {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 clock-frequency = <24576000>;
0027 };
0028
0029 enet_ext: oscillator-ethernet {
0030 compatible = "fixed-clock";
0031 #clock-cells = <0>;
0032 clock-frequency = <50000000>;
0033 };
0034
0035 leds {
0036 compatible = "gpio-leds";
0037 pinctrl-names = "default";
0038 pinctrl-0 = <&pinctrl_gpio_leds>;
0039
0040 /* LED D5 */
0041 led0: heartbeat {
0042 label = "heartbeat";
0043 gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
0044 default-state = "on";
0045 linux,default-trigger = "heartbeat";
0046 };
0047 };
0048
0049 reg_3p3v: regulator-3p3v {
0050 compatible = "regulator-fixed";
0051 regulator-name = "3P3V";
0052 regulator-min-microvolt = <3300000>;
0053 regulator-max-microvolt = <3300000>;
0054 regulator-always-on;
0055 };
0056
0057 reg_vcc_3v3_mcu: regulator-vcc3v3mcu {
0058 compatible = "regulator-fixed";
0059 regulator-name = "vcc_3v3_mcu";
0060 regulator-min-microvolt = <3300000>;
0061 regulator-max-microvolt = <3300000>;
0062 };
0063
0064 spi-gpio {
0065 compatible = "spi-gpio";
0066 pinctrl-0 = <&pinctrl_gpio_spi>;
0067 pinctrl-names = "default";
0068 #address-cells = <1>;
0069 #size-cells = <0>;
0070 /* PTD12 ->RPIO[91] */
0071 sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
0072 /* PTD10 ->RPIO[89] */
0073 miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
0074 num-chipselects = <0>;
0075
0076 gpio@0 {
0077 compatible = "pisosr-gpio";
0078 reg = <0>;
0079 gpio-controller;
0080 #gpio-cells = <2>;
0081 /* PTB18 -> RGPIO[40] */
0082 load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
0083 spi-max-frequency = <100000>;
0084 };
0085 };
0086 };
0087
0088 &adc0 {
0089 vref-supply = <®_vcc_3v3_mcu>;
0090 status = "okay";
0091 };
0092
0093 &adc1 {
0094 vref-supply = <®_vcc_3v3_mcu>;
0095 status = "okay";
0096 };
0097
0098 &can0 {
0099 pinctrl-names = "default";
0100 pinctrl-0 = <&pinctrl_can0>;
0101 status = "okay";
0102 };
0103
0104 &can1 {
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&pinctrl_can1>;
0107 status = "okay";
0108 };
0109
0110 &clks {
0111 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
0112 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
0113 };
0114
0115 &dspi0 {
0116 pinctrl-names = "default";
0117 pinctrl-0 = <&pinctrl_dspi0>;
0118 bus-num = <0>;
0119 status = "okay";
0120
0121 spidev0@0 {
0122 compatible = "lwn,bk4";
0123 spi-max-frequency = <30000000>;
0124 reg = <0>;
0125 fsl,spi-cs-sck-delay = <200>;
0126 fsl,spi-sck-cs-delay = <400>;
0127 };
0128 };
0129
0130 &dspi3 {
0131 pinctrl-names = "default";
0132 pinctrl-0 = <&pinctrl_dspi3>;
0133 bus-num = <3>;
0134 status = "okay";
0135 spi-slave;
0136 #address-cells = <0>;
0137
0138 slave {
0139 compatible = "lwn,bk4";
0140 spi-max-frequency = <30000000>;
0141 };
0142 };
0143
0144 &edma0 {
0145 status = "okay";
0146 };
0147
0148 &edma1 {
0149 status = "okay";
0150 };
0151
0152 &esdhc1 {
0153 pinctrl-names = "default";
0154 pinctrl-0 = <&pinctrl_esdhc1>;
0155 bus-width = <4>;
0156 cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
0157 status = "okay";
0158 };
0159
0160 &fec0 {
0161 phy-mode = "rmii";
0162 phy-handle = <ðphy0>;
0163 pinctrl-names = "default";
0164 pinctrl-0 = <&pinctrl_fec0>;
0165 status = "okay";
0166
0167 mdio {
0168 #address-cells = <1>;
0169 #size-cells = <0>;
0170
0171 ethphy0: ethernet-phy@1 {
0172 reg = <1>;
0173 clocks = <&clks VF610_CLK_ENET_50M>;
0174 clock-names = "rmii-ref";
0175 };
0176 };
0177 };
0178
0179 &fec1 {
0180 phy-mode = "rmii";
0181 phy-handle = <ðphy1>;
0182 pinctrl-names = "default";
0183 pinctrl-0 = <&pinctrl_fec1>;
0184 status = "okay";
0185
0186 mdio {
0187 #address-cells = <1>;
0188 #size-cells = <0>;
0189
0190 ethphy1: ethernet-phy@1 {
0191 reg = <1>;
0192 clocks = <&clks VF610_CLK_ENET_50M>;
0193 clock-names = "rmii-ref";
0194 };
0195 };
0196 };
0197
0198 &i2c2 {
0199 clock-frequency = <400000>;
0200 pinctrl-names = "default";
0201 pinctrl-0 = <&pinctrl_i2c2>;
0202 status = "okay";
0203
0204 at24c256: eeprom@50 {
0205 compatible = "atmel,24c256";
0206 reg = <0x50>;
0207 };
0208
0209 m41t62: rtc@68 {
0210 compatible = "st,m41t62";
0211 reg = <0x68>;
0212 };
0213 };
0214
0215 &nfc {
0216 assigned-clocks = <&clks VF610_CLK_NFC>;
0217 assigned-clock-rates = <33000000>;
0218 pinctrl-names = "default";
0219 pinctrl-0 = <&pinctrl_nfc>;
0220 status = "okay";
0221
0222 nand@0 {
0223 compatible = "fsl,vf610-nfc-nandcs";
0224 reg = <0>;
0225 #address-cells = <1>;
0226 #size-cells = <1>;
0227 nand-bus-width = <16>;
0228 nand-ecc-mode = "hw";
0229 nand-ecc-strength = <24>;
0230 nand-ecc-step-size = <2048>;
0231 nand-on-flash-bbt;
0232 };
0233 };
0234
0235 &qspi0 {
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_qspi0>;
0238 status = "okay";
0239
0240 n25q128a13_4: flash@0 {
0241 compatible = "n25q128a13", "jedec,spi-nor";
0242 #address-cells = <1>;
0243 #size-cells = <1>;
0244 spi-max-frequency = <66000000>;
0245 spi-rx-bus-width = <4>;
0246 reg = <0>;
0247 };
0248
0249 n25q128a13_2: flash@2 {
0250 compatible = "n25q128a13", "jedec,spi-nor";
0251 #address-cells = <1>;
0252 #size-cells = <1>;
0253 spi-max-frequency = <66000000>;
0254 spi-rx-bus-width = <2>;
0255 reg = <2>;
0256 };
0257 };
0258
0259 &uart0 {
0260 pinctrl-names = "default";
0261 pinctrl-0 = <&pinctrl_uart0>;
0262 /delete-property/dma-names;
0263 status = "okay";
0264 };
0265
0266 &uart1 {
0267 pinctrl-names = "default";
0268 pinctrl-0 = <&pinctrl_uart1>;
0269 /delete-property/dma-names;
0270 status = "okay";
0271 };
0272
0273 &uart2 {
0274 pinctrl-names = "default";
0275 pinctrl-0 = <&pinctrl_uart2>;
0276 /delete-property/dma-names;
0277 status = "okay";
0278 };
0279
0280 &uart3 {
0281 pinctrl-names = "default";
0282 pinctrl-0 = <&pinctrl_uart3>;
0283 /delete-property/dma-names;
0284 status = "okay";
0285 };
0286
0287 &usbdev0 {
0288 disable-over-current;
0289 status = "okay";
0290 };
0291
0292 &usbh1 {
0293 disable-over-current;
0294 status = "okay";
0295 };
0296
0297 &usbmisc0 {
0298 status = "okay";
0299 };
0300
0301 &usbmisc1 {
0302 status = "okay";
0303 };
0304
0305 &usbphy0 {
0306 status = "okay";
0307 };
0308
0309 &usbphy1 {
0310 status = "okay";
0311 };
0312
0313 &iomuxc {
0314 pinctrl-names = "default";
0315 pinctrl-0 = <&pinctrl_hog>;
0316
0317 pinctrl_hog: hoggrp {
0318 fsl,pins = <
0319 /* One_Wire_PSU_EN */
0320 VF610_PAD_PTC29__GPIO_102 0x1183
0321 /* SPI ENABLE */
0322 VF610_PAD_PTB26__GPIO_96 0x1183
0323 /* EB control */
0324 VF610_PAD_PTE14__GPIO_119 0x1183
0325 VF610_PAD_PTE4__GPIO_109 0x1181
0326 /* Feedback_Lines */
0327 VF610_PAD_PTC31__GPIO_104 0x1181
0328 VF610_PAD_PTA7__GPIO_134 0x1181
0329 VF610_PAD_PTD9__GPIO_88 0x1181
0330 VF610_PAD_PTE1__GPIO_106 0x1183
0331 VF610_PAD_PTB2__GPIO_24 0x1181
0332 VF610_PAD_PTB3__GPIO_25 0x1181
0333 VF610_PAD_PTB1__GPIO_23 0x1181
0334 /* SDHC Enable */
0335 VF610_PAD_PTE19__GPIO_124 0x1183
0336 /* SDHC Overcurrent */
0337 VF610_PAD_PTB23__GPIO_93 0x1181
0338 /* GPI */
0339 VF610_PAD_PTE2__GPIO_107 0x1181
0340 VF610_PAD_PTE3__GPIO_108 0x1181
0341 VF610_PAD_PTE5__GPIO_110 0x1181
0342 VF610_PAD_PTE6__GPIO_111 0x1181
0343 /* GPO */
0344 VF610_PAD_PTE0__GPIO_105 0x1183
0345 VF610_PAD_PTE7__GPIO_112 0x1183
0346 /* RS485 Control */
0347 VF610_PAD_PTB8__GPIO_30 0x1183
0348 VF610_PAD_PTB9__GPIO_31 0x1183
0349 VF610_PAD_PTE8__GPIO_113 0x1183
0350 /* MPBUS MPB_EN */
0351 VF610_PAD_PTE28__GPIO_133 0x1183
0352 /* MISC */
0353 VF610_PAD_PTE10__GPIO_115 0x1183
0354 VF610_PAD_PTE11__GPIO_116 0x1183
0355 VF610_PAD_PTE17__GPIO_122 0x1183
0356 VF610_PAD_PTC30__GPIO_103 0x1183
0357 VF610_PAD_PTB0__GPIO_22 0x1181
0358 /* RESETINFO */
0359 VF610_PAD_PTE26__GPIO_131 0x1183
0360 VF610_PAD_PTD6__GPIO_85 0x1181
0361 VF610_PAD_PTE27__GPIO_132 0x1181
0362 VF610_PAD_PTE13__GPIO_118 0x1181
0363 VF610_PAD_PTE21__GPIO_126 0x1181
0364 VF610_PAD_PTE22__GPIO_127 0x1181
0365 /* EE_5V_EN */
0366 VF610_PAD_PTE18__GPIO_123 0x1183
0367 /* EE_5V_OC_N */
0368 VF610_PAD_PTE25__GPIO_130 0x1181
0369 >;
0370 };
0371
0372 pinctrl_can0: can0grp {
0373 fsl,pins = <
0374 VF610_PAD_PTB14__CAN0_RX 0x1181
0375 VF610_PAD_PTB15__CAN0_TX 0x1182
0376 >;
0377 };
0378
0379 pinctrl_can1: can1grp {
0380 fsl,pins = <
0381 VF610_PAD_PTB16__CAN1_RX 0x1181
0382 VF610_PAD_PTB17__CAN1_TX 0x1182
0383 >;
0384 };
0385
0386 pinctrl_dspi0: dspi0grp {
0387 fsl,pins = <
0388 VF610_PAD_PTB18__DSPI0_CS1 0x1182
0389 VF610_PAD_PTB19__DSPI0_CS0 0x1182
0390 VF610_PAD_PTB20__DSPI0_SIN 0x1181
0391 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
0392 VF610_PAD_PTB22__DSPI0_SCK 0x1182
0393 >;
0394 };
0395
0396 pinctrl_dspi3: dspi3grp {
0397 fsl,pins = <
0398 VF610_PAD_PTD10__DSPI3_CS0 0x1181
0399 VF610_PAD_PTD11__DSPI3_SIN 0x1181
0400 VF610_PAD_PTD12__DSPI3_SOUT 0x1182
0401 VF610_PAD_PTD13__DSPI3_SCK 0x1181
0402 >;
0403 };
0404
0405 pinctrl_esdhc1: esdhc1grp {
0406 fsl,pins = <
0407 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
0408 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
0409 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
0410 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
0411 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
0412 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
0413 VF610_PAD_PTB28__GPIO_98 0x219d
0414 >;
0415 };
0416
0417 pinctrl_fec0: fec0grp {
0418 fsl,pins = <
0419 VF610_PAD_PTA6__RMII_CLKIN 0x30dd
0420 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de
0421 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
0422 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd
0423 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
0424 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
0425 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
0426 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
0427 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
0428 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
0429 >;
0430 };
0431
0432 pinctrl_fec1: fec1grp {
0433 fsl,pins = <
0434 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de
0435 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df
0436 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd
0437 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd
0438 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd
0439 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd
0440 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de
0441 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de
0442 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de
0443 >;
0444 };
0445
0446 pinctrl_gpio_leds: gpioledsgrp {
0447 fsl,pins = <
0448 /* Heart bit LED */
0449 VF610_PAD_PTE12__GPIO_117 0x1183
0450 /* LEDS */
0451 VF610_PAD_PTE15__GPIO_120 0x1183
0452 VF610_PAD_PTA12__GPIO_5 0x1183
0453 VF610_PAD_PTA16__GPIO_6 0x1183
0454 VF610_PAD_PTE9__GPIO_114 0x1183
0455 VF610_PAD_PTE20__GPIO_125 0x1183
0456 VF610_PAD_PTE23__GPIO_128 0x1183
0457 VF610_PAD_PTE16__GPIO_121 0x1183
0458 >;
0459 };
0460
0461 pinctrl_gpio_spi: pinctrl-gpio-spi {
0462 fsl,pins = <
0463 VF610_PAD_PTB18__GPIO_40 0x1183
0464 VF610_PAD_PTD10__GPIO_89 0x1183
0465 VF610_PAD_PTD12__GPIO_91 0x1183
0466 >;
0467 };
0468
0469 pinctrl_i2c2: i2c2grp {
0470 fsl,pins = <
0471 VF610_PAD_PTA22__I2C2_SCL 0x34df
0472 VF610_PAD_PTA23__I2C2_SDA 0x34df
0473 >;
0474 };
0475
0476 pinctrl_nfc: nfcgrp {
0477 fsl,pins = <
0478 VF610_PAD_PTD23__NF_IO7 0x28df
0479 VF610_PAD_PTD22__NF_IO6 0x28df
0480 VF610_PAD_PTD21__NF_IO5 0x28df
0481 VF610_PAD_PTD20__NF_IO4 0x28df
0482 VF610_PAD_PTD19__NF_IO3 0x28df
0483 VF610_PAD_PTD18__NF_IO2 0x28df
0484 VF610_PAD_PTD17__NF_IO1 0x28df
0485 VF610_PAD_PTD16__NF_IO0 0x28df
0486 VF610_PAD_PTB24__NF_WE_B 0x28c2
0487 VF610_PAD_PTB25__NF_CE0_B 0x28c2
0488 VF610_PAD_PTB27__NF_RE_B 0x28c2
0489 VF610_PAD_PTC26__NF_RB_B 0x283d
0490 VF610_PAD_PTC27__NF_ALE 0x28c2
0491 VF610_PAD_PTC28__NF_CLE 0x28c2
0492 >;
0493 };
0494
0495 pinctrl_qspi0: qspi0grp {
0496 fsl,pins = <
0497 VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f
0498 VF610_PAD_PTD1__QSPI0_A_CS0 0x397f
0499 VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f
0500 VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f
0501 VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f
0502 VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f
0503 VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f
0504 VF610_PAD_PTD8__QSPI0_B_CS0 0x397f
0505 VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f
0506 VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f
0507 >;
0508 };
0509
0510 pinctrl_uart0: uart0grp {
0511 fsl,pins = <
0512 VF610_PAD_PTB10__UART0_TX 0x21a2
0513 VF610_PAD_PTB11__UART0_RX 0x21a1
0514 >;
0515 };
0516
0517 pinctrl_uart1: uart1grp {
0518 fsl,pins = <
0519 VF610_PAD_PTB4__UART1_TX 0x21a2
0520 VF610_PAD_PTB5__UART1_RX 0x21a1
0521 >;
0522 };
0523
0524 pinctrl_uart2: uart2grp {
0525 fsl,pins = <
0526 VF610_PAD_PTB6__UART2_TX 0x21a2
0527 VF610_PAD_PTB7__UART2_RX 0x21a1
0528 >;
0529 };
0530
0531 pinctrl_uart3: uart3grp {
0532 fsl,pins = <
0533 VF610_PAD_PTA20__UART3_TX 0x21a2
0534 VF610_PAD_PTA21__UART3_RX 0x21a1
0535 >;
0536 };
0537 };
