0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 //
0003 // Copyright 2013 Freescale Semiconductor, Inc.
0004
0005 #include "vfxxx.dtsi"
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 chosen { };
0012 aliases { };
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017
0018 a5_cpu: cpu@0 {
0019 compatible = "arm,cortex-a5";
0020 device_type = "cpu";
0021 reg = <0x0>;
0022 };
0023 };
0024
0025 soc {
0026 bus@40000000 {
0027
0028 intc: interrupt-controller@40003000 {
0029 compatible = "arm,cortex-a9-gic";
0030 #interrupt-cells = <3>;
0031 interrupt-controller;
0032 interrupt-parent = <&intc>;
0033 reg = <0x40003000 0x1000>,
0034 <0x40002100 0x100>;
0035 };
0036
0037 global_timer: timer@40002200 {
0038 compatible = "arm,cortex-a9-global-timer";
0039 reg = <0x40002200 0x20>;
0040 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
0041 interrupt-parent = <&intc>;
0042 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
0043 };
0044 };
0045
0046 bus@40080000 {
0047 pmu@40089000 {
0048 compatible = "arm,cortex-a5-pmu";
0049 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
0050 interrupt-affinity = <&a5_cpu>;
0051 reg = <0x40089000 0x1000>;
0052 };
0053 };
0054
0055 };
0056 };
0057
0058 &mscm_ir {
0059 interrupt-parent = <&intc>;
0060 };
0061
0062 &wdoga5 {
0063 status = "okay";
0064 };
