0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 /*
0003 * Copyright 2014-2020 Toradex
0004 *
0005 */
0006
0007 / {
0008 aliases {
0009 ethernet0 = &fec1;
0010 ethernet1 = &fec0;
0011 };
0012
0013 bl: backlight {
0014 compatible = "pwm-backlight";
0015 pinctrl-names = "default";
0016 pinctrl-0 = <&pinctrl_gpio_bl_on>;
0017 pwms = <&pwm0 0 5000000 0>;
0018 enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
0019 status = "disabled";
0020 };
0021
0022 reg_module_3v3: regulator-module-3v3 {
0023 compatible = "regulator-fixed";
0024 regulator-name = "+V3.3";
0025 regulator-min-microvolt = <3300000>;
0026 regulator-max-microvolt = <3300000>;
0027 };
0028
0029 reg_module_3v3_avdd: regulator-module-3v3-avdd {
0030 compatible = "regulator-fixed";
0031 regulator-name = "+V3.3_AVDD_AUDIO";
0032 regulator-min-microvolt = <3300000>;
0033 regulator-max-microvolt = <3300000>;
0034 };
0035 };
0036
0037 &adc0 {
0038 status = "okay";
0039 vref-supply = <®_module_3v3_avdd>;
0040 };
0041
0042 &adc1 {
0043 status = "okay";
0044 vref-supply = <®_module_3v3_avdd>;
0045 };
0046
0047 &can0 {
0048 pinctrl-names = "default";
0049 pinctrl-0 = <&pinctrl_flexcan0>;
0050 status = "disabled";
0051 };
0052
0053 &can1 {
0054 pinctrl-names = "default";
0055 pinctrl-0 = <&pinctrl_flexcan1>;
0056 status = "disabled";
0057 };
0058
0059 &clks {
0060 assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
0061 <&clks VF610_CLK_ENET_TS_SEL>;
0062 assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
0063 <&clks VF610_CLK_ENET_50M>;
0064 };
0065
0066 &dspi1 {
0067 bus-num = <1>;
0068 pinctrl-names = "default";
0069 pinctrl-0 = <&pinctrl_dspi1>;
0070 };
0071
0072 &edma0 {
0073 status = "okay";
0074 };
0075
0076 &edma1 {
0077 status = "okay";
0078 };
0079
0080 &esdhc1 {
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&pinctrl_esdhc1>;
0083 bus-width = <4>;
0084 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
0085 disable-wp;
0086 };
0087
0088 &fec1 {
0089 phy-mode = "rmii";
0090 phy-supply = <®_module_3v3>;
0091 pinctrl-names = "default";
0092 pinctrl-0 = <&pinctrl_fec1>;
0093 };
0094
0095 &i2c0 {
0096 clock-frequency = <400000>;
0097 pinctrl-names = "default", "gpio";
0098 pinctrl-0 = <&pinctrl_i2c0>;
0099 pinctrl-1 = <&pinctrl_i2c0_gpio>;
0100 scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0101 sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0102 };
0103
0104 &nfc {
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&pinctrl_nfc>;
0107 status = "okay";
0108
0109 nand@0 {
0110 compatible = "fsl,vf610-nfc-nandcs";
0111 reg = <0>;
0112 #address-cells = <1>;
0113 #size-cells = <1>;
0114 nand-bus-width = <8>;
0115 nand-ecc-mode = "hw";
0116 nand-ecc-strength = <32>;
0117 nand-ecc-step-size = <2048>;
0118 nand-on-flash-bbt;
0119 };
0120 };
0121
0122 &pwm0 {
0123 pinctrl-names = "default";
0124 pinctrl-0 = <&pinctrl_pwm0>;
0125 };
0126
0127 &pwm1 {
0128 pinctrl-names = "default";
0129 pinctrl-0 = <&pinctrl_pwm1>;
0130 };
0131
0132 &uart0 {
0133 pinctrl-names = "default";
0134 pinctrl-0 = <&pinctrl_uart0>;
0135 };
0136
0137 &uart1 {
0138 pinctrl-names = "default";
0139 pinctrl-0 = <&pinctrl_uart1>;
0140 };
0141
0142 &uart2 {
0143 pinctrl-names = "default";
0144 pinctrl-0 = <&pinctrl_uart2>;
0145 };
0146
0147 &usbdev0 {
0148 disable-over-current;
0149 status = "okay";
0150 };
0151
0152 &usbh1 {
0153 disable-over-current;
0154 status = "okay";
0155 };
0156
0157 &usbmisc0 {
0158 status = "okay";
0159 };
0160
0161 &usbmisc1 {
0162 status = "okay";
0163 };
0164
0165 &usbphy0 {
0166 status = "okay";
0167 };
0168
0169 &usbphy1 {
0170 status = "okay";
0171 };
0172
0173 &iomuxc {
0174 vf610-colibri {
0175 pinctrl_flexcan0: can0grp {
0176 fsl,pins = <
0177 VF610_PAD_PTB14__CAN0_RX 0x31F1
0178 VF610_PAD_PTB15__CAN0_TX 0x31F2
0179 >;
0180 };
0181
0182 pinctrl_flexcan1: can1grp {
0183 fsl,pins = <
0184 VF610_PAD_PTB16__CAN1_RX 0x31F1
0185 VF610_PAD_PTB17__CAN1_TX 0x31F2
0186 >;
0187 };
0188
0189 pinctrl_gpio_ext: gpio_ext {
0190 fsl,pins = <
0191 VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
0192 VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
0193 VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
0194 >;
0195 };
0196
0197 pinctrl_dcu0_1: dcu0grp_1 {
0198 fsl,pins = <
0199 VF610_PAD_PTE0__DCU0_HSYNC 0x1902
0200 VF610_PAD_PTE1__DCU0_VSYNC 0x1902
0201 VF610_PAD_PTE2__DCU0_PCLK 0x1902
0202 VF610_PAD_PTE4__DCU0_DE 0x1902
0203 VF610_PAD_PTE5__DCU0_R0 0x1902
0204 VF610_PAD_PTE6__DCU0_R1 0x1902
0205 VF610_PAD_PTE7__DCU0_R2 0x1902
0206 VF610_PAD_PTE8__DCU0_R3 0x1902
0207 VF610_PAD_PTE9__DCU0_R4 0x1902
0208 VF610_PAD_PTE10__DCU0_R5 0x1902
0209 VF610_PAD_PTE11__DCU0_R6 0x1902
0210 VF610_PAD_PTE12__DCU0_R7 0x1902
0211 VF610_PAD_PTE13__DCU0_G0 0x1902
0212 VF610_PAD_PTE14__DCU0_G1 0x1902
0213 VF610_PAD_PTE15__DCU0_G2 0x1902
0214 VF610_PAD_PTE16__DCU0_G3 0x1902
0215 VF610_PAD_PTE17__DCU0_G4 0x1902
0216 VF610_PAD_PTE18__DCU0_G5 0x1902
0217 VF610_PAD_PTE19__DCU0_G6 0x1902
0218 VF610_PAD_PTE20__DCU0_G7 0x1902
0219 VF610_PAD_PTE21__DCU0_B0 0x1902
0220 VF610_PAD_PTE22__DCU0_B1 0x1902
0221 VF610_PAD_PTE23__DCU0_B2 0x1902
0222 VF610_PAD_PTE24__DCU0_B3 0x1902
0223 VF610_PAD_PTE25__DCU0_B4 0x1902
0224 VF610_PAD_PTE26__DCU0_B5 0x1902
0225 VF610_PAD_PTE27__DCU0_B6 0x1902
0226 VF610_PAD_PTE28__DCU0_B7 0x1902
0227 >;
0228 };
0229
0230 pinctrl_dspi1: dspi1grp {
0231 fsl,pins = <
0232 VF610_PAD_PTD5__DSPI1_CS0 0x33e2
0233 VF610_PAD_PTD6__DSPI1_SIN 0x33e1
0234 VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
0235 VF610_PAD_PTD8__DSPI1_SCK 0x33e2
0236 >;
0237 };
0238
0239 pinctrl_esdhc1: esdhc1grp {
0240 fsl,pins = <
0241 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
0242 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
0243 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
0244 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
0245 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
0246 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
0247 VF610_PAD_PTB20__GPIO_42 0x219d
0248 >;
0249 };
0250
0251 pinctrl_fec1: fec1grp {
0252 fsl,pins = <
0253 VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
0254 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
0255 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
0256 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
0257 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
0258 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
0259 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
0260 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
0261 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
0262 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
0263 >;
0264 };
0265
0266 pinctrl_gpio_bl_on: gpio_bl_on {
0267 fsl,pins = <
0268 VF610_PAD_PTC0__GPIO_45 0x22ef
0269 >;
0270 };
0271
0272 pinctrl_i2c0: i2c0grp {
0273 fsl,pins = <
0274 VF610_PAD_PTB14__I2C0_SCL 0x37ff
0275 VF610_PAD_PTB15__I2C0_SDA 0x37ff
0276 >;
0277 };
0278
0279 pinctrl_i2c0_gpio: i2c0gpiogrp {
0280 fsl,pins = <
0281 VF610_PAD_PTB14__GPIO_36 0x37ff
0282 VF610_PAD_PTB15__GPIO_37 0x37ff
0283 >;
0284 };
0285
0286 pinctrl_nfc: nfcgrp {
0287 fsl,pins = <
0288 VF610_PAD_PTD23__NF_IO7 0x28df
0289 VF610_PAD_PTD22__NF_IO6 0x28df
0290 VF610_PAD_PTD21__NF_IO5 0x28df
0291 VF610_PAD_PTD20__NF_IO4 0x28df
0292 VF610_PAD_PTD19__NF_IO3 0x28df
0293 VF610_PAD_PTD18__NF_IO2 0x28df
0294 VF610_PAD_PTD17__NF_IO1 0x28df
0295 VF610_PAD_PTD16__NF_IO0 0x28df
0296 VF610_PAD_PTB24__NF_WE_B 0x28c2
0297 VF610_PAD_PTB25__NF_CE0_B 0x28c2
0298 VF610_PAD_PTB27__NF_RE_B 0x28c2
0299 VF610_PAD_PTC26__NF_RB_B 0x283d
0300 VF610_PAD_PTC27__NF_ALE 0x28c2
0301 VF610_PAD_PTC28__NF_CLE 0x28c2
0302 >;
0303 };
0304
0305 pinctrl_pwm0: pwm0grp {
0306 fsl,pins = <
0307 VF610_PAD_PTB0__FTM0_CH0 0x1182
0308 VF610_PAD_PTB1__FTM0_CH1 0x1182
0309 >;
0310 };
0311
0312 pinctrl_pwm1: pwm1grp {
0313 fsl,pins = <
0314 VF610_PAD_PTB8__FTM1_CH0 0x1182
0315 VF610_PAD_PTB9__FTM1_CH1 0x1182
0316 >;
0317 };
0318
0319 pinctrl_uart0: uart0grp {
0320 fsl,pins = <
0321 VF610_PAD_PTB10__UART0_TX 0x21a2
0322 VF610_PAD_PTB11__UART0_RX 0x21a1
0323 VF610_PAD_PTB12__UART0_RTS 0x21a2
0324 VF610_PAD_PTB13__UART0_CTS 0x21a1
0325 >;
0326 };
0327
0328 pinctrl_uart1: uart1grp {
0329 fsl,pins = <
0330 VF610_PAD_PTB4__UART1_TX 0x21a2
0331 VF610_PAD_PTB5__UART1_RX 0x21a1
0332 >;
0333 };
0334
0335 pinctrl_uart2: uart2grp {
0336 fsl,pins = <
0337 VF610_PAD_PTD0__UART2_TX 0x21a2
0338 VF610_PAD_PTD1__UART2_RX 0x21a1
0339 VF610_PAD_PTD2__UART2_RTS 0x21a2
0340 VF610_PAD_PTD3__UART2_CTS 0x21a1
0341 >;
0342 };
0343
0344 pinctrl_usbh1_reg: gpio_usb_vbus {
0345 fsl,pins = <
0346 VF610_PAD_PTD4__GPIO_83 0x22ed
0347 >;
0348 };
0349 };
0350 };
