0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Versatile Express
0004 *
0005 * CoreTile Express A9x4
0006 * Cortex-A9 MPCore (V2P-CA9)
0007 *
0008 * HBI-0191B
0009 */
0010
0011 /dts-v1/;
0012 #include "vexpress-v2m.dtsi"
0013
0014 / {
0015 model = "V2P-CA9";
0016 arm,hbi = <0x191>;
0017 arm,vexpress,site = <0xf>;
0018 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
0019 interrupt-parent = <&gic>;
0020 #address-cells = <1>;
0021 #size-cells = <1>;
0022
0023 chosen { };
0024
0025 aliases {
0026 serial0 = &v2m_serial0;
0027 serial1 = &v2m_serial1;
0028 serial2 = &v2m_serial2;
0029 serial3 = &v2m_serial3;
0030 i2c0 = &v2m_i2c_dvi;
0031 i2c1 = &v2m_i2c_pcie;
0032 };
0033
0034 cpus {
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037
0038 A9_0: cpu@0 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a9";
0041 reg = <0>;
0042 next-level-cache = <&L2>;
0043 };
0044
0045 A9_1: cpu@1 {
0046 device_type = "cpu";
0047 compatible = "arm,cortex-a9";
0048 reg = <1>;
0049 next-level-cache = <&L2>;
0050 };
0051
0052 A9_2: cpu@2 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a9";
0055 reg = <2>;
0056 next-level-cache = <&L2>;
0057 };
0058
0059 A9_3: cpu@3 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a9";
0062 reg = <3>;
0063 next-level-cache = <&L2>;
0064 };
0065 };
0066
0067 memory@60000000 {
0068 device_type = "memory";
0069 reg = <0x60000000 0x40000000>;
0070 };
0071
0072 reserved-memory {
0073 #address-cells = <1>;
0074 #size-cells = <1>;
0075 ranges;
0076
0077 /* Chipselect 3 is physically at 0x4c000000 */
0078 vram: vram@4c000000 {
0079 /* 8 MB of designated video RAM */
0080 compatible = "shared-dma-pool";
0081 reg = <0x4c000000 0x00800000>;
0082 no-map;
0083 };
0084 };
0085
0086 clcd@10020000 {
0087 compatible = "arm,pl111", "arm,primecell";
0088 reg = <0x10020000 0x1000>;
0089 interrupt-names = "combined";
0090 interrupts = <0 44 4>;
0091 clocks = <&oscclk1>, <&oscclk2>;
0092 clock-names = "clcdclk", "apb_pclk";
0093 /* 1024x768 16bpp @65MHz */
0094 max-memory-bandwidth = <95000000>;
0095
0096 port {
0097 clcd_pads_ct: endpoint {
0098 remote-endpoint = <&dvi_bridge_in_ct>;
0099 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0100 };
0101 };
0102 };
0103
0104 memory-controller@100e0000 {
0105 compatible = "arm,pl341", "arm,primecell";
0106 reg = <0x100e0000 0x1000>;
0107 clocks = <&oscclk2>;
0108 clock-names = "apb_pclk";
0109 };
0110
0111 memory-controller@100e1000 {
0112 compatible = "arm,pl354", "arm,primecell";
0113 reg = <0x100e1000 0x1000>;
0114 interrupts = <0 45 4>,
0115 <0 46 4>;
0116 clocks = <&oscclk2>;
0117 clock-names = "apb_pclk";
0118 };
0119
0120 timer@100e4000 {
0121 compatible = "arm,sp804", "arm,primecell";
0122 reg = <0x100e4000 0x1000>;
0123 interrupts = <0 48 4>,
0124 <0 49 4>;
0125 clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>;
0126 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0127 status = "disabled";
0128 };
0129
0130 watchdog@100e5000 {
0131 compatible = "arm,sp805", "arm,primecell";
0132 reg = <0x100e5000 0x1000>;
0133 interrupts = <0 51 4>;
0134 clocks = <&oscclk2>, <&oscclk2>;
0135 clock-names = "wdog_clk", "apb_pclk";
0136 };
0137
0138 scu@1e000000 {
0139 compatible = "arm,cortex-a9-scu";
0140 reg = <0x1e000000 0x58>;
0141 };
0142
0143 timer@1e000600 {
0144 compatible = "arm,cortex-a9-twd-timer";
0145 reg = <0x1e000600 0x20>;
0146 interrupts = <1 13 0xf04>;
0147 };
0148
0149 watchdog@1e000620 {
0150 compatible = "arm,cortex-a9-twd-wdt";
0151 reg = <0x1e000620 0x20>;
0152 interrupts = <1 14 0xf04>;
0153 };
0154
0155 gic: interrupt-controller@1e001000 {
0156 compatible = "arm,cortex-a9-gic";
0157 #interrupt-cells = <3>;
0158 #address-cells = <0>;
0159 interrupt-controller;
0160 reg = <0x1e001000 0x1000>,
0161 <0x1e000100 0x100>;
0162 };
0163
0164 L2: cache-controller@1e00a000 {
0165 compatible = "arm,pl310-cache";
0166 reg = <0x1e00a000 0x1000>;
0167 interrupts = <0 43 4>;
0168 cache-unified;
0169 cache-level = <2>;
0170 arm,data-latency = <1 1 1>;
0171 arm,tag-latency = <1 1 1>;
0172 };
0173
0174 pmu {
0175 compatible = "arm,cortex-a9-pmu";
0176 interrupts = <0 60 4>,
0177 <0 61 4>,
0178 <0 62 4>,
0179 <0 63 4>;
0180 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
0181
0182 };
0183
0184 dcc {
0185 compatible = "arm,vexpress,config-bus";
0186 arm,vexpress,config-bridge = <&v2m_sysreg>;
0187
0188 oscclk0: extsaxiclk {
0189 /* ACLK clock to the AXI master port on the test chip */
0190 compatible = "arm,vexpress-osc";
0191 arm,vexpress-sysreg,func = <1 0>;
0192 freq-range = <30000000 50000000>;
0193 #clock-cells = <0>;
0194 clock-output-names = "extsaxiclk";
0195 };
0196
0197 oscclk1: clcdclk {
0198 /* Reference clock for the CLCD */
0199 compatible = "arm,vexpress-osc";
0200 arm,vexpress-sysreg,func = <1 1>;
0201 freq-range = <10000000 80000000>;
0202 #clock-cells = <0>;
0203 clock-output-names = "clcdclk";
0204 };
0205
0206 smbclk: oscclk2: tcrefclk {
0207 /* Reference clock for the test chip internal PLLs */
0208 compatible = "arm,vexpress-osc";
0209 arm,vexpress-sysreg,func = <1 2>;
0210 freq-range = <33000000 100000000>;
0211 #clock-cells = <0>;
0212 clock-output-names = "tcrefclk";
0213 };
0214
0215 volt-vd10 {
0216 /* Test Chip internal logic voltage */
0217 compatible = "arm,vexpress-volt";
0218 arm,vexpress-sysreg,func = <2 0>;
0219 regulator-name = "VD10";
0220 regulator-always-on;
0221 label = "VD10";
0222 };
0223
0224 volt-vd10-s2 {
0225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
0226 compatible = "arm,vexpress-volt";
0227 arm,vexpress-sysreg,func = <2 1>;
0228 regulator-name = "VD10_S2";
0229 regulator-always-on;
0230 label = "VD10_S2";
0231 };
0232
0233 volt-vd10-s3 {
0234 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
0235 compatible = "arm,vexpress-volt";
0236 arm,vexpress-sysreg,func = <2 2>;
0237 regulator-name = "VD10_S3";
0238 regulator-always-on;
0239 label = "VD10_S3";
0240 };
0241
0242 volt-vcc1v8 {
0243 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
0244 compatible = "arm,vexpress-volt";
0245 arm,vexpress-sysreg,func = <2 3>;
0246 regulator-name = "VCC1V8";
0247 regulator-always-on;
0248 label = "VCC1V8";
0249 };
0250
0251 volt-ddr2vtt {
0252 /* DDR2 SDRAM VTT termination voltage */
0253 compatible = "arm,vexpress-volt";
0254 arm,vexpress-sysreg,func = <2 4>;
0255 regulator-name = "DDR2VTT";
0256 regulator-always-on;
0257 label = "DDR2VTT";
0258 };
0259
0260 volt-vcc3v3 {
0261 /* Local board supply for miscellaneous logic external to the Test Chip */
0262 arm,vexpress-sysreg,func = <2 5>;
0263 compatible = "arm,vexpress-volt";
0264 regulator-name = "VCC3V3";
0265 regulator-always-on;
0266 label = "VCC3V3";
0267 };
0268
0269 amp-vd10-s2 {
0270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
0271 compatible = "arm,vexpress-amp";
0272 arm,vexpress-sysreg,func = <3 0>;
0273 label = "VD10_S2";
0274 };
0275
0276 amp-vd10-s3 {
0277 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
0278 compatible = "arm,vexpress-amp";
0279 arm,vexpress-sysreg,func = <3 1>;
0280 label = "VD10_S3";
0281 };
0282
0283 power-vd10-s2 {
0284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
0285 compatible = "arm,vexpress-power";
0286 arm,vexpress-sysreg,func = <12 0>;
0287 label = "PVD10_S2";
0288 };
0289
0290 power-vd10-s3 {
0291 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
0292 compatible = "arm,vexpress-power";
0293 arm,vexpress-sysreg,func = <12 1>;
0294 label = "PVD10_S3";
0295 };
0296 };
0297
0298 site2: hsb@e0000000 {
0299 compatible = "simple-bus";
0300 #address-cells = <1>;
0301 #size-cells = <1>;
0302 ranges = <0 0xe0000000 0x20000000>;
0303 #interrupt-cells = <1>;
0304 interrupt-map-mask = <0 3>;
0305 interrupt-map = <0 0 &gic 0 36 4>,
0306 <0 1 &gic 0 37 4>,
0307 <0 2 &gic 0 38 4>,
0308 <0 3 &gic 0 39 4>;
0309 };
0310 };
