0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Versatile Express
0004 *
0005 * CoreTile Express A5x2
0006 * Cortex-A5 MPCore (V2P-CA5s)
0007 *
0008 * HBI-0225B
0009 */
0010
0011 /dts-v1/;
0012 #include "vexpress-v2m-rs1.dtsi"
0013
0014 / {
0015 model = "V2P-CA5s";
0016 arm,hbi = <0x225>;
0017 arm,vexpress,site = <0xf>;
0018 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
0019 interrupt-parent = <&gic>;
0020 #address-cells = <1>;
0021 #size-cells = <1>;
0022
0023 chosen { };
0024
0025 aliases {
0026 serial0 = &v2m_serial0;
0027 serial1 = &v2m_serial1;
0028 serial2 = &v2m_serial2;
0029 serial3 = &v2m_serial3;
0030 i2c0 = &v2m_i2c_dvi;
0031 i2c1 = &v2m_i2c_pcie;
0032 };
0033
0034 cpus {
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037
0038 cpu@0 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a5";
0041 reg = <0>;
0042 next-level-cache = <&L2>;
0043 };
0044
0045 cpu@1 {
0046 device_type = "cpu";
0047 compatible = "arm,cortex-a5";
0048 reg = <1>;
0049 next-level-cache = <&L2>;
0050 };
0051 };
0052
0053 memory@80000000 {
0054 device_type = "memory";
0055 reg = <0x80000000 0x40000000>;
0056 };
0057
0058 reserved-memory {
0059 #address-cells = <1>;
0060 #size-cells = <1>;
0061 ranges;
0062
0063 /* Chipselect 2 is physically at 0x18000000 */
0064 vram: vram@18000000 {
0065 /* 8 MB of designated video RAM */
0066 compatible = "shared-dma-pool";
0067 reg = <0x18000000 0x00800000>;
0068 no-map;
0069 };
0070 };
0071
0072 hdlcd@2a110000 {
0073 compatible = "arm,hdlcd";
0074 reg = <0x2a110000 0x1000>;
0075 interrupts = <0 85 4>;
0076 clocks = <&hdlcd_clk>;
0077 clock-names = "pxlclk";
0078 };
0079
0080 memory-controller@2a150000 {
0081 compatible = "arm,pl341", "arm,primecell";
0082 reg = <0x2a150000 0x1000>;
0083 clocks = <&axi_clk>;
0084 clock-names = "apb_pclk";
0085 };
0086
0087 memory-controller@2a190000 {
0088 compatible = "arm,pl354", "arm,primecell";
0089 reg = <0x2a190000 0x1000>;
0090 interrupts = <0 86 4>,
0091 <0 87 4>;
0092 clocks = <&axi_clk>;
0093 clock-names = "apb_pclk";
0094 };
0095
0096 scu@2c000000 {
0097 compatible = "arm,cortex-a5-scu";
0098 reg = <0x2c000000 0x58>;
0099 };
0100
0101 timer@2c000600 {
0102 compatible = "arm,cortex-a5-twd-timer";
0103 reg = <0x2c000600 0x20>;
0104 interrupts = <1 13 0x304>;
0105 };
0106
0107 timer@2c000200 {
0108 compatible = "arm,cortex-a5-global-timer",
0109 "arm,cortex-a9-global-timer";
0110 reg = <0x2c000200 0x20>;
0111 interrupts = <1 11 0x304>;
0112 clocks = <&cpu_clk>;
0113 };
0114
0115 watchdog@2c000620 {
0116 compatible = "arm,cortex-a5-twd-wdt";
0117 reg = <0x2c000620 0x20>;
0118 interrupts = <1 14 0x304>;
0119 };
0120
0121 gic: interrupt-controller@2c001000 {
0122 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
0123 #interrupt-cells = <3>;
0124 #address-cells = <0>;
0125 interrupt-controller;
0126 reg = <0x2c001000 0x1000>,
0127 <0x2c000100 0x100>;
0128 };
0129
0130 L2: cache-controller@2c0f0000 {
0131 compatible = "arm,pl310-cache";
0132 reg = <0x2c0f0000 0x1000>;
0133 interrupts = <0 84 4>;
0134 cache-level = <2>;
0135 };
0136
0137 pmu {
0138 compatible = "arm,cortex-a5-pmu";
0139 interrupts = <0 68 4>,
0140 <0 69 4>;
0141 };
0142
0143 dcc {
0144 compatible = "arm,vexpress,config-bus";
0145 arm,vexpress,config-bridge = <&v2m_sysreg>;
0146
0147 cpu_clk: oscclk0 {
0148 /* CPU and internal AXI reference clock */
0149 compatible = "arm,vexpress-osc";
0150 arm,vexpress-sysreg,func = <1 0>;
0151 freq-range = <50000000 100000000>;
0152 #clock-cells = <0>;
0153 clock-output-names = "oscclk0";
0154 };
0155
0156 axi_clk: oscclk1 {
0157 /* Multiplexed AXI master clock */
0158 compatible = "arm,vexpress-osc";
0159 arm,vexpress-sysreg,func = <1 1>;
0160 freq-range = <5000000 50000000>;
0161 #clock-cells = <0>;
0162 clock-output-names = "oscclk1";
0163 };
0164
0165 oscclk2 {
0166 /* DDR2 */
0167 compatible = "arm,vexpress-osc";
0168 arm,vexpress-sysreg,func = <1 2>;
0169 freq-range = <80000000 120000000>;
0170 #clock-cells = <0>;
0171 clock-output-names = "oscclk2";
0172 };
0173
0174 hdlcd_clk: oscclk3 {
0175 /* HDLCD */
0176 compatible = "arm,vexpress-osc";
0177 arm,vexpress-sysreg,func = <1 3>;
0178 freq-range = <23750000 165000000>;
0179 #clock-cells = <0>;
0180 clock-output-names = "oscclk3";
0181 };
0182
0183 oscclk4 {
0184 /* Test chip gate configuration */
0185 compatible = "arm,vexpress-osc";
0186 arm,vexpress-sysreg,func = <1 4>;
0187 freq-range = <80000000 80000000>;
0188 #clock-cells = <0>;
0189 clock-output-names = "oscclk4";
0190 };
0191
0192 smbclk: oscclk5 {
0193 /* SMB clock */
0194 compatible = "arm,vexpress-osc";
0195 arm,vexpress-sysreg,func = <1 5>;
0196 freq-range = <25000000 60000000>;
0197 #clock-cells = <0>;
0198 clock-output-names = "oscclk5";
0199 };
0200
0201 temp-dcc {
0202 /* DCC internal operating temperature */
0203 compatible = "arm,vexpress-temp";
0204 arm,vexpress-sysreg,func = <4 0>;
0205 label = "DCC";
0206 };
0207 };
0208
0209 smb: bus@8000000 {
0210 ranges = <0 0x8000000 0x18000000>;
0211 };
0212
0213 site2: hsb@40000000 {
0214 compatible = "simple-bus";
0215 #address-cells = <1>;
0216 #size-cells = <1>;
0217 ranges = <0 0x40000000 0x40000000>;
0218 #interrupt-cells = <1>;
0219 interrupt-map-mask = <0 3>;
0220 interrupt-map = <0 0 &gic 0 36 4>,
0221 <0 1 &gic 0 37 4>,
0222 <0 2 &gic 0 38 4>,
0223 <0 3 &gic 0 39 4>;
0224 };
0225 };
