0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Versatile Express
0004 *
0005 * CoreTile Express A15x2 A7x3
0006 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
0007 *
0008 * HBI-0249A
0009 */
0010
0011 /dts-v1/;
0012 #include "vexpress-v2m-rs1.dtsi"
0013
0014 / {
0015 model = "V2P-CA15_CA7";
0016 arm,hbi = <0x249>;
0017 arm,vexpress,site = <0xf>;
0018 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
0019 interrupt-parent = <&gic>;
0020 #address-cells = <2>;
0021 #size-cells = <2>;
0022
0023 chosen { };
0024
0025 aliases {
0026 serial0 = &v2m_serial0;
0027 serial1 = &v2m_serial1;
0028 serial2 = &v2m_serial2;
0029 serial3 = &v2m_serial3;
0030 i2c0 = &v2m_i2c_dvi;
0031 i2c1 = &v2m_i2c_pcie;
0032 };
0033
0034 cpus {
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037
0038 cpu0: cpu@0 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a15";
0041 reg = <0>;
0042 cci-control-port = <&cci_control1>;
0043 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
0044 capacity-dmips-mhz = <1024>;
0045 dynamic-power-coefficient = <990>;
0046 };
0047
0048 cpu1: cpu@1 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a15";
0051 reg = <1>;
0052 cci-control-port = <&cci_control1>;
0053 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
0054 capacity-dmips-mhz = <1024>;
0055 dynamic-power-coefficient = <990>;
0056 };
0057
0058 cpu2: cpu@2 {
0059 device_type = "cpu";
0060 compatible = "arm,cortex-a7";
0061 reg = <0x100>;
0062 cci-control-port = <&cci_control2>;
0063 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
0064 capacity-dmips-mhz = <516>;
0065 dynamic-power-coefficient = <133>;
0066 };
0067
0068 cpu3: cpu@3 {
0069 device_type = "cpu";
0070 compatible = "arm,cortex-a7";
0071 reg = <0x101>;
0072 cci-control-port = <&cci_control2>;
0073 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
0074 capacity-dmips-mhz = <516>;
0075 dynamic-power-coefficient = <133>;
0076 };
0077
0078 cpu4: cpu@4 {
0079 device_type = "cpu";
0080 compatible = "arm,cortex-a7";
0081 reg = <0x102>;
0082 cci-control-port = <&cci_control2>;
0083 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
0084 capacity-dmips-mhz = <516>;
0085 dynamic-power-coefficient = <133>;
0086 };
0087
0088 idle-states {
0089 CLUSTER_SLEEP_BIG: cluster-sleep-big {
0090 compatible = "arm,idle-state";
0091 local-timer-stop;
0092 entry-latency-us = <1000>;
0093 exit-latency-us = <700>;
0094 min-residency-us = <2000>;
0095 };
0096
0097 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
0098 compatible = "arm,idle-state";
0099 local-timer-stop;
0100 entry-latency-us = <1000>;
0101 exit-latency-us = <500>;
0102 min-residency-us = <2500>;
0103 };
0104 };
0105 };
0106
0107 memory@80000000 {
0108 device_type = "memory";
0109 reg = <0 0x80000000 0 0x40000000>;
0110 };
0111
0112 reserved-memory {
0113 #address-cells = <2>;
0114 #size-cells = <2>;
0115 ranges;
0116
0117 /* Chipselect 2 is physically at 0x18000000 */
0118 vram: vram@18000000 {
0119 /* 8 MB of designated video RAM */
0120 compatible = "shared-dma-pool";
0121 reg = <0 0x18000000 0 0x00800000>;
0122 no-map;
0123 };
0124 };
0125
0126 wdt@2a490000 {
0127 compatible = "arm,sp805", "arm,primecell";
0128 reg = <0 0x2a490000 0 0x1000>;
0129 interrupts = <0 98 4>;
0130 clocks = <&oscclk6a>, <&oscclk6a>;
0131 clock-names = "wdog_clk", "apb_pclk";
0132 };
0133
0134 hdlcd@2b000000 {
0135 compatible = "arm,hdlcd";
0136 reg = <0 0x2b000000 0 0x1000>;
0137 interrupts = <0 85 4>;
0138 clocks = <&hdlcd_clk>;
0139 clock-names = "pxlclk";
0140 };
0141
0142 memory-controller@2b0a0000 {
0143 compatible = "arm,pl341", "arm,primecell";
0144 reg = <0 0x2b0a0000 0 0x1000>;
0145 clocks = <&oscclk6a>;
0146 clock-names = "apb_pclk";
0147 };
0148
0149 gic: interrupt-controller@2c001000 {
0150 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
0151 #interrupt-cells = <3>;
0152 #address-cells = <0>;
0153 interrupt-controller;
0154 reg = <0 0x2c001000 0 0x1000>,
0155 <0 0x2c002000 0 0x2000>,
0156 <0 0x2c004000 0 0x2000>,
0157 <0 0x2c006000 0 0x2000>;
0158 interrupts = <1 9 0xf04>;
0159 };
0160
0161 cci@2c090000 {
0162 compatible = "arm,cci-400";
0163 #address-cells = <1>;
0164 #size-cells = <1>;
0165 reg = <0 0x2c090000 0 0x1000>;
0166 ranges = <0x0 0x0 0x2c090000 0x10000>;
0167
0168 cci_control1: slave-if@4000 {
0169 compatible = "arm,cci-400-ctrl-if";
0170 interface-type = "ace";
0171 reg = <0x4000 0x1000>;
0172 };
0173
0174 cci_control2: slave-if@5000 {
0175 compatible = "arm,cci-400-ctrl-if";
0176 interface-type = "ace";
0177 reg = <0x5000 0x1000>;
0178 };
0179
0180 pmu@9000 {
0181 compatible = "arm,cci-400-pmu,r0";
0182 reg = <0x9000 0x5000>;
0183 interrupts = <0 105 4>,
0184 <0 101 4>,
0185 <0 102 4>,
0186 <0 103 4>,
0187 <0 104 4>;
0188 };
0189 };
0190
0191 memory-controller@7ffd0000 {
0192 compatible = "arm,pl354", "arm,primecell";
0193 reg = <0 0x7ffd0000 0 0x1000>;
0194 interrupts = <0 86 4>,
0195 <0 87 4>;
0196 clocks = <&oscclk6a>;
0197 clock-names = "apb_pclk";
0198 };
0199
0200 dma@7ff00000 {
0201 compatible = "arm,pl330", "arm,primecell";
0202 reg = <0 0x7ff00000 0 0x1000>;
0203 interrupts = <0 92 4>,
0204 <0 88 4>,
0205 <0 89 4>,
0206 <0 90 4>,
0207 <0 91 4>;
0208 clocks = <&oscclk6a>;
0209 clock-names = "apb_pclk";
0210 };
0211
0212 scc@7fff0000 {
0213 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
0214 reg = <0 0x7fff0000 0 0x1000>;
0215 interrupts = <0 95 4>;
0216 };
0217
0218 timer {
0219 compatible = "arm,armv7-timer";
0220 interrupts = <1 13 0xf08>,
0221 <1 14 0xf08>,
0222 <1 11 0xf08>,
0223 <1 10 0xf08>;
0224 };
0225
0226 pmu-a15 {
0227 compatible = "arm,cortex-a15-pmu";
0228 interrupts = <0 68 4>,
0229 <0 69 4>;
0230 interrupt-affinity = <&cpu0>,
0231 <&cpu1>;
0232 };
0233
0234 pmu-a7 {
0235 compatible = "arm,cortex-a7-pmu";
0236 interrupts = <0 128 4>,
0237 <0 129 4>,
0238 <0 130 4>;
0239 interrupt-affinity = <&cpu2>,
0240 <&cpu3>,
0241 <&cpu4>;
0242 };
0243
0244 oscclk6a: oscclk6a {
0245 /* Reference 24MHz clock */
0246 compatible = "fixed-clock";
0247 #clock-cells = <0>;
0248 clock-frequency = <24000000>;
0249 clock-output-names = "oscclk6a";
0250 };
0251
0252 dcc {
0253 compatible = "arm,vexpress,config-bus";
0254 arm,vexpress,config-bridge = <&v2m_sysreg>;
0255
0256 oscclk0 {
0257 /* A15 PLL 0 reference clock */
0258 compatible = "arm,vexpress-osc";
0259 arm,vexpress-sysreg,func = <1 0>;
0260 freq-range = <17000000 50000000>;
0261 #clock-cells = <0>;
0262 clock-output-names = "oscclk0";
0263 };
0264
0265 oscclk1 {
0266 /* A15 PLL 1 reference clock */
0267 compatible = "arm,vexpress-osc";
0268 arm,vexpress-sysreg,func = <1 1>;
0269 freq-range = <17000000 50000000>;
0270 #clock-cells = <0>;
0271 clock-output-names = "oscclk1";
0272 };
0273
0274 oscclk2 {
0275 /* A7 PLL 0 reference clock */
0276 compatible = "arm,vexpress-osc";
0277 arm,vexpress-sysreg,func = <1 2>;
0278 freq-range = <17000000 50000000>;
0279 #clock-cells = <0>;
0280 clock-output-names = "oscclk2";
0281 };
0282
0283 oscclk3 {
0284 /* A7 PLL 1 reference clock */
0285 compatible = "arm,vexpress-osc";
0286 arm,vexpress-sysreg,func = <1 3>;
0287 freq-range = <17000000 50000000>;
0288 #clock-cells = <0>;
0289 clock-output-names = "oscclk3";
0290 };
0291
0292 oscclk4 {
0293 /* External AXI master clock */
0294 compatible = "arm,vexpress-osc";
0295 arm,vexpress-sysreg,func = <1 4>;
0296 freq-range = <20000000 40000000>;
0297 #clock-cells = <0>;
0298 clock-output-names = "oscclk4";
0299 };
0300
0301 hdlcd_clk: oscclk5 {
0302 /* HDLCD PLL reference clock */
0303 compatible = "arm,vexpress-osc";
0304 arm,vexpress-sysreg,func = <1 5>;
0305 freq-range = <23750000 165000000>;
0306 #clock-cells = <0>;
0307 clock-output-names = "oscclk5";
0308 };
0309
0310 smbclk: oscclk6 {
0311 /* Static memory controller clock */
0312 compatible = "arm,vexpress-osc";
0313 arm,vexpress-sysreg,func = <1 6>;
0314 freq-range = <20000000 40000000>;
0315 #clock-cells = <0>;
0316 clock-output-names = "oscclk6";
0317 };
0318
0319 oscclk7 {
0320 /* SYS PLL reference clock */
0321 compatible = "arm,vexpress-osc";
0322 arm,vexpress-sysreg,func = <1 7>;
0323 freq-range = <17000000 50000000>;
0324 #clock-cells = <0>;
0325 clock-output-names = "oscclk7";
0326 };
0327
0328 oscclk8 {
0329 /* DDR2 PLL reference clock */
0330 compatible = "arm,vexpress-osc";
0331 arm,vexpress-sysreg,func = <1 8>;
0332 freq-range = <20000000 50000000>;
0333 #clock-cells = <0>;
0334 clock-output-names = "oscclk8";
0335 };
0336
0337 volt-a15 {
0338 /* A15 CPU core voltage */
0339 compatible = "arm,vexpress-volt";
0340 arm,vexpress-sysreg,func = <2 0>;
0341 regulator-name = "A15 Vcore";
0342 regulator-min-microvolt = <800000>;
0343 regulator-max-microvolt = <1050000>;
0344 regulator-always-on;
0345 label = "A15 Vcore";
0346 };
0347
0348 volt-a7 {
0349 /* A7 CPU core voltage */
0350 compatible = "arm,vexpress-volt";
0351 arm,vexpress-sysreg,func = <2 1>;
0352 regulator-name = "A7 Vcore";
0353 regulator-min-microvolt = <800000>;
0354 regulator-max-microvolt = <1050000>;
0355 regulator-always-on;
0356 label = "A7 Vcore";
0357 };
0358
0359 amp-a15 {
0360 /* Total current for the two A15 cores */
0361 compatible = "arm,vexpress-amp";
0362 arm,vexpress-sysreg,func = <3 0>;
0363 label = "A15 Icore";
0364 };
0365
0366 amp-a7 {
0367 /* Total current for the three A7 cores */
0368 compatible = "arm,vexpress-amp";
0369 arm,vexpress-sysreg,func = <3 1>;
0370 label = "A7 Icore";
0371 };
0372
0373 temp-dcc {
0374 /* DCC internal temperature */
0375 compatible = "arm,vexpress-temp";
0376 arm,vexpress-sysreg,func = <4 0>;
0377 label = "DCC";
0378 };
0379
0380 power-a15 {
0381 /* Total power for the two A15 cores */
0382 compatible = "arm,vexpress-power";
0383 arm,vexpress-sysreg,func = <12 0>;
0384 label = "A15 Pcore";
0385 };
0386
0387 power-a7 {
0388 /* Total power for the three A7 cores */
0389 compatible = "arm,vexpress-power";
0390 arm,vexpress-sysreg,func = <12 1>;
0391 label = "A7 Pcore";
0392 };
0393
0394 energy-a15 {
0395 /* Total energy for the two A15 cores */
0396 compatible = "arm,vexpress-energy";
0397 arm,vexpress-sysreg,func = <13 0>, <13 1>;
0398 label = "A15 Jcore";
0399 };
0400
0401 energy-a7 {
0402 /* Total energy for the three A7 cores */
0403 compatible = "arm,vexpress-energy";
0404 arm,vexpress-sysreg,func = <13 2>, <13 3>;
0405 label = "A7 Jcore";
0406 };
0407 };
0408
0409 etb@20010000 {
0410 compatible = "arm,coresight-etb10", "arm,primecell";
0411 reg = <0 0x20010000 0 0x1000>;
0412
0413 clocks = <&oscclk6a>;
0414 clock-names = "apb_pclk";
0415 in-ports {
0416 port {
0417 etb_in_port: endpoint {
0418 remote-endpoint = <&replicator_out_port0>;
0419 };
0420 };
0421 };
0422 };
0423
0424 tpiu@20030000 {
0425 compatible = "arm,coresight-tpiu", "arm,primecell";
0426 reg = <0 0x20030000 0 0x1000>;
0427
0428 clocks = <&oscclk6a>;
0429 clock-names = "apb_pclk";
0430 in-ports {
0431 port {
0432 tpiu_in_port: endpoint {
0433 remote-endpoint = <&replicator_out_port1>;
0434 };
0435 };
0436 };
0437 };
0438
0439 replicator {
0440 /* non-configurable replicators don't show up on the
0441 * AMBA bus. As such no need to add "arm,primecell".
0442 */
0443 compatible = "arm,coresight-static-replicator";
0444
0445 out-ports {
0446 #address-cells = <1>;
0447 #size-cells = <0>;
0448
0449 port@0 {
0450 reg = <0>;
0451 replicator_out_port0: endpoint {
0452 remote-endpoint = <&etb_in_port>;
0453 };
0454 };
0455
0456 port@1 {
0457 reg = <1>;
0458 replicator_out_port1: endpoint {
0459 remote-endpoint = <&tpiu_in_port>;
0460 };
0461 };
0462 };
0463
0464 in-ports {
0465 port {
0466 replicator_in_port0: endpoint {
0467 remote-endpoint = <&funnel_out_port0>;
0468 };
0469 };
0470 };
0471 };
0472
0473 funnel@20040000 {
0474 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0475 reg = <0 0x20040000 0 0x1000>;
0476
0477 clocks = <&oscclk6a>;
0478 clock-names = "apb_pclk";
0479 out-ports {
0480 port {
0481 funnel_out_port0: endpoint {
0482 remote-endpoint =
0483 <&replicator_in_port0>;
0484 };
0485 };
0486 };
0487
0488 in-ports {
0489 #address-cells = <1>;
0490 #size-cells = <0>;
0491
0492 port@0 {
0493 reg = <0>;
0494 funnel_in_port0: endpoint {
0495 remote-endpoint = <&ptm0_out_port>;
0496 };
0497 };
0498
0499 port@1 {
0500 reg = <1>;
0501 funnel_in_port1: endpoint {
0502 remote-endpoint = <&ptm1_out_port>;
0503 };
0504 };
0505
0506 port@2 {
0507 reg = <2>;
0508 funnel_in_port2: endpoint {
0509 remote-endpoint = <&etm0_out_port>;
0510 };
0511 };
0512
0513 /* Input port #3 is for ITM, not supported here */
0514
0515 port@4 {
0516 reg = <4>;
0517 funnel_in_port4: endpoint {
0518 remote-endpoint = <&etm1_out_port>;
0519 };
0520 };
0521
0522 port@5 {
0523 reg = <5>;
0524 funnel_in_port5: endpoint {
0525 remote-endpoint = <&etm2_out_port>;
0526 };
0527 };
0528 };
0529 };
0530
0531 ptm@2201c000 {
0532 compatible = "arm,coresight-etm3x", "arm,primecell";
0533 reg = <0 0x2201c000 0 0x1000>;
0534
0535 cpu = <&cpu0>;
0536 clocks = <&oscclk6a>;
0537 clock-names = "apb_pclk";
0538 out-ports {
0539 port {
0540 ptm0_out_port: endpoint {
0541 remote-endpoint = <&funnel_in_port0>;
0542 };
0543 };
0544 };
0545 };
0546
0547 ptm@2201d000 {
0548 compatible = "arm,coresight-etm3x", "arm,primecell";
0549 reg = <0 0x2201d000 0 0x1000>;
0550
0551 cpu = <&cpu1>;
0552 clocks = <&oscclk6a>;
0553 clock-names = "apb_pclk";
0554 out-ports {
0555 port {
0556 ptm1_out_port: endpoint {
0557 remote-endpoint = <&funnel_in_port1>;
0558 };
0559 };
0560 };
0561 };
0562
0563 etm@2203c000 {
0564 compatible = "arm,coresight-etm3x", "arm,primecell";
0565 reg = <0 0x2203c000 0 0x1000>;
0566
0567 cpu = <&cpu2>;
0568 clocks = <&oscclk6a>;
0569 clock-names = "apb_pclk";
0570 out-ports {
0571 port {
0572 etm0_out_port: endpoint {
0573 remote-endpoint = <&funnel_in_port2>;
0574 };
0575 };
0576 };
0577 };
0578
0579 etm@2203d000 {
0580 compatible = "arm,coresight-etm3x", "arm,primecell";
0581 reg = <0 0x2203d000 0 0x1000>;
0582
0583 cpu = <&cpu3>;
0584 clocks = <&oscclk6a>;
0585 clock-names = "apb_pclk";
0586 out-ports {
0587 port {
0588 etm1_out_port: endpoint {
0589 remote-endpoint = <&funnel_in_port4>;
0590 };
0591 };
0592 };
0593 };
0594
0595 etm@2203e000 {
0596 compatible = "arm,coresight-etm3x", "arm,primecell";
0597 reg = <0 0x2203e000 0 0x1000>;
0598
0599 cpu = <&cpu4>;
0600 clocks = <&oscclk6a>;
0601 clock-names = "apb_pclk";
0602 out-ports {
0603 port {
0604 etm2_out_port: endpoint {
0605 remote-endpoint = <&funnel_in_port5>;
0606 };
0607 };
0608 };
0609 };
0610
0611 smb: bus@8000000 {
0612 ranges = <0x8000000 0 0x8000000 0x18000000>;
0613 };
0614
0615 site2: hsb@40000000 {
0616 compatible = "simple-bus";
0617 #address-cells = <1>;
0618 #size-cells = <1>;
0619 ranges = <0 0 0x40000000 0x3fef0000>;
0620 #interrupt-cells = <1>;
0621 interrupt-map-mask = <0 3>;
0622 interrupt-map = <0 0 &gic 0 36 4>,
0623 <0 1 &gic 0 37 4>,
0624 <0 2 &gic 0 38 4>,
0625 <0 3 &gic 0 39 4>;
0626 };
0627 };
0628
0629 &nor_flash {
0630 /*
0631 * Unfortunately, accessing the flash disturbs the CPU idle states
0632 * (suspend) and CPU hotplug of this platform. For this reason, flash
0633 * hardware access is disabled by default on this platform alone.
0634 */
0635 status = "disabled";
0636 };
