0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Versatile Express
0004 *
0005 * CoreTile Express A15x2 (version with Test Chip 1)
0006 * Cortex-A15 MPCore (V2P-CA15)
0007 *
0008 * HBI-0237A
0009 */
0010
0011 /dts-v1/;
0012 #include "vexpress-v2m-rs1.dtsi"
0013
0014 / {
0015 model = "V2P-CA15";
0016 arm,hbi = <0x237>;
0017 arm,vexpress,site = <0xf>;
0018 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
0019 interrupt-parent = <&gic>;
0020 #address-cells = <2>;
0021 #size-cells = <2>;
0022
0023 chosen { };
0024
0025 aliases {
0026 serial0 = &v2m_serial0;
0027 serial1 = &v2m_serial1;
0028 serial2 = &v2m_serial2;
0029 serial3 = &v2m_serial3;
0030 i2c0 = &v2m_i2c_dvi;
0031 i2c1 = &v2m_i2c_pcie;
0032 };
0033
0034 cpus {
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037
0038 cpu@0 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a15";
0041 reg = <0>;
0042 };
0043
0044 cpu@1 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a15";
0047 reg = <1>;
0048 };
0049 };
0050
0051 memory@80000000 {
0052 device_type = "memory";
0053 reg = <0 0x80000000 0 0x40000000>;
0054 };
0055
0056 reserved-memory {
0057 #address-cells = <2>;
0058 #size-cells = <2>;
0059 ranges;
0060
0061 /* Chipselect 2 is physically at 0x18000000 */
0062 vram: vram@18000000 {
0063 /* 8 MB of designated video RAM */
0064 compatible = "shared-dma-pool";
0065 reg = <0 0x18000000 0 0x00800000>;
0066 no-map;
0067 };
0068 };
0069
0070 hdlcd@2b000000 {
0071 compatible = "arm,hdlcd";
0072 reg = <0 0x2b000000 0 0x1000>;
0073 interrupts = <0 85 4>;
0074 clocks = <&hdlcd_clk>;
0075 clock-names = "pxlclk";
0076 };
0077
0078 memory-controller@2b0a0000 {
0079 compatible = "arm,pl341", "arm,primecell";
0080 reg = <0 0x2b0a0000 0 0x1000>;
0081 clocks = <&sys_pll>;
0082 clock-names = "apb_pclk";
0083 };
0084
0085 wdt@2b060000 {
0086 compatible = "arm,sp805", "arm,primecell";
0087 status = "disabled";
0088 reg = <0 0x2b060000 0 0x1000>;
0089 interrupts = <0 98 4>;
0090 clocks = <&sys_pll>, <&sys_pll>;
0091 clock-names = "wdog_clk", "apb_pclk";
0092 };
0093
0094 gic: interrupt-controller@2c001000 {
0095 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
0096 #interrupt-cells = <3>;
0097 #address-cells = <0>;
0098 interrupt-controller;
0099 reg = <0 0x2c001000 0 0x1000>,
0100 <0 0x2c002000 0 0x2000>,
0101 <0 0x2c004000 0 0x2000>,
0102 <0 0x2c006000 0 0x2000>;
0103 interrupts = <1 9 0xf04>;
0104 };
0105
0106 memory-controller@7ffd0000 {
0107 compatible = "arm,pl354", "arm,primecell";
0108 reg = <0 0x7ffd0000 0 0x1000>;
0109 interrupts = <0 86 4>,
0110 <0 87 4>;
0111 clocks = <&sys_pll>;
0112 clock-names = "apb_pclk";
0113 };
0114
0115 dma@7ffb0000 {
0116 compatible = "arm,pl330", "arm,primecell";
0117 reg = <0 0x7ffb0000 0 0x1000>;
0118 interrupts = <0 92 4>,
0119 <0 88 4>,
0120 <0 89 4>,
0121 <0 90 4>,
0122 <0 91 4>;
0123 clocks = <&sys_pll>;
0124 clock-names = "apb_pclk";
0125 };
0126
0127 timer {
0128 compatible = "arm,armv7-timer";
0129 interrupts = <1 13 0xf08>,
0130 <1 14 0xf08>,
0131 <1 11 0xf08>,
0132 <1 10 0xf08>;
0133 };
0134
0135 pmu {
0136 compatible = "arm,cortex-a15-pmu";
0137 interrupts = <0 68 4>,
0138 <0 69 4>;
0139 };
0140
0141 dcc {
0142 compatible = "arm,vexpress,config-bus";
0143 arm,vexpress,config-bridge = <&v2m_sysreg>;
0144
0145 oscclk0 {
0146 /* CPU PLL reference clock */
0147 compatible = "arm,vexpress-osc";
0148 arm,vexpress-sysreg,func = <1 0>;
0149 freq-range = <50000000 60000000>;
0150 #clock-cells = <0>;
0151 clock-output-names = "oscclk0";
0152 };
0153
0154 oscclk4 {
0155 /* Multiplexed AXI master clock */
0156 compatible = "arm,vexpress-osc";
0157 arm,vexpress-sysreg,func = <1 4>;
0158 freq-range = <20000000 40000000>;
0159 #clock-cells = <0>;
0160 clock-output-names = "oscclk4";
0161 };
0162
0163 hdlcd_clk: oscclk5 {
0164 /* HDLCD PLL reference clock */
0165 compatible = "arm,vexpress-osc";
0166 arm,vexpress-sysreg,func = <1 5>;
0167 freq-range = <23750000 165000000>;
0168 #clock-cells = <0>;
0169 clock-output-names = "oscclk5";
0170 };
0171
0172 smbclk: oscclk6 {
0173 /* SMB clock */
0174 compatible = "arm,vexpress-osc";
0175 arm,vexpress-sysreg,func = <1 6>;
0176 freq-range = <20000000 50000000>;
0177 #clock-cells = <0>;
0178 clock-output-names = "oscclk6";
0179 };
0180
0181 sys_pll: oscclk7 {
0182 /* SYS PLL reference clock */
0183 compatible = "arm,vexpress-osc";
0184 arm,vexpress-sysreg,func = <1 7>;
0185 freq-range = <20000000 60000000>;
0186 #clock-cells = <0>;
0187 clock-output-names = "oscclk7";
0188 };
0189
0190 oscclk8 {
0191 /* DDR2 PLL reference clock */
0192 compatible = "arm,vexpress-osc";
0193 arm,vexpress-sysreg,func = <1 8>;
0194 freq-range = <40000000 40000000>;
0195 #clock-cells = <0>;
0196 clock-output-names = "oscclk8";
0197 };
0198
0199 volt-cores {
0200 /* CPU core voltage */
0201 compatible = "arm,vexpress-volt";
0202 arm,vexpress-sysreg,func = <2 0>;
0203 regulator-name = "Cores";
0204 regulator-min-microvolt = <800000>;
0205 regulator-max-microvolt = <1050000>;
0206 regulator-always-on;
0207 label = "Cores";
0208 };
0209
0210 amp-cores {
0211 /* Total current for the two cores */
0212 compatible = "arm,vexpress-amp";
0213 arm,vexpress-sysreg,func = <3 0>;
0214 label = "Cores";
0215 };
0216
0217 temp-dcc {
0218 /* DCC internal temperature */
0219 compatible = "arm,vexpress-temp";
0220 arm,vexpress-sysreg,func = <4 0>;
0221 label = "DCC";
0222 };
0223
0224 power-cores {
0225 /* Total power */
0226 compatible = "arm,vexpress-power";
0227 arm,vexpress-sysreg,func = <12 0>;
0228 label = "Cores";
0229 };
0230
0231 energy {
0232 /* Total energy */
0233 compatible = "arm,vexpress-energy";
0234 arm,vexpress-sysreg,func = <13 0>;
0235 label = "Cores";
0236 };
0237 };
0238
0239 bus@8000000 {
0240 ranges = <0x8000000 0 0x8000000 0x18000000>;
0241 };
0242
0243 site2: hsb@40000000 {
0244 compatible = "simple-bus";
0245 #address-cells = <1>;
0246 #size-cells = <1>;
0247 ranges = <0 0 0x40000000 0x3fef0000>;
0248 #interrupt-cells = <1>;
0249 interrupt-map-mask = <0 3>;
0250 interrupt-map = <0 0 &gic 0 36 4>,
0251 <0 1 &gic 0 37 4>,
0252 <0 2 &gic 0 38 4>,
0253 <0 3 &gic 0 39 4>;
0254 };
0255 };
