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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Versatile Express
0004 *
0005 * Motherboard Express uATX
0006 * V2M-P1
0007 *
0008 * HBI-0190D
0009 *
0010 * Original memory map ("Legacy memory map" in the board's
0011 * Technical Reference Manual)
0012 *
0013 * WARNING! The hardware described in this file is independent from the
0014 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
0015 * correspondence between the two configurations.
0016 *
0017 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
0018 * CHANGES TO vexpress-v2m-rs1.dtsi!
0019 */
0020 #include <dt-bindings/interrupt-controller/arm-gic.h>
0021
0022 / {
0023 bus@40000000 {
0024 compatible = "simple-bus";
0025 #address-cells = <1>;
0026 #size-cells = <1>;
0027 ranges = <0x40000000 0x40000000 0x10000000>,
0028 <0x10000000 0x10000000 0x00020000>;
0029
0030 #interrupt-cells = <1>;
0031 interrupt-map-mask = <0 63>;
0032 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0033 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0034 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0035 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0036 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0037 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0038 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0039 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0040 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0041 <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0042 <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0043 <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0044 <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0045 <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0046 <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0047 <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0048 <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0049 <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0050 <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0051 <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0052 <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0053 <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0054 <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0055 <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0056 <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0057 <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0058 <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0059 <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0060 <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0061 <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0062 <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0063 <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
0064 <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0065 <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0066 <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0067 <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0068 <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0069 <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0070 <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0071 <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0072 <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0073 <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0074 <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0075
0076 motherboard-bus@40000000 {
0077 arm,hbi = <0x190>;
0078 arm,vexpress,site = <0>;
0079 compatible = "arm,vexpress,v2m-p1", "simple-bus";
0080 #address-cells = <2>; /* SMB chipselect number and offset */
0081 #size-cells = <1>;
0082 ranges = <0 0 0x40000000 0x04000000>,
0083 <1 0 0x44000000 0x04000000>,
0084 <2 0 0x48000000 0x04000000>,
0085 <3 0 0x4c000000 0x04000000>,
0086 <7 0 0x10000000 0x00020000>;
0087
0088 flash@0,00000000 {
0089 compatible = "arm,vexpress-flash", "cfi-flash";
0090 reg = <0 0x00000000 0x04000000>,
0091 <1 0x00000000 0x04000000>;
0092 bank-width = <4>;
0093 partitions {
0094 compatible = "arm,arm-firmware-suite";
0095 };
0096 };
0097
0098 psram@2,00000000 {
0099 compatible = "arm,vexpress-psram", "mtd-ram";
0100 reg = <2 0x00000000 0x02000000>;
0101 bank-width = <4>;
0102 };
0103
0104 ethernet@3,02000000 {
0105 compatible = "smsc,lan9118", "smsc,lan9115";
0106 reg = <3 0x02000000 0x10000>;
0107 interrupts = <15>;
0108 phy-mode = "mii";
0109 reg-io-width = <4>;
0110 smsc,irq-active-high;
0111 smsc,irq-push-pull;
0112 vdd33a-supply = <&v2m_fixed_3v3>;
0113 vddvario-supply = <&v2m_fixed_3v3>;
0114 };
0115
0116 usb@3,03000000 {
0117 compatible = "nxp,usb-isp1761";
0118 reg = <3 0x03000000 0x20000>;
0119 interrupts = <16>;
0120 dr_mode = "peripheral";
0121 };
0122
0123 iofpga@7,00000000 {
0124 compatible = "simple-bus";
0125 #address-cells = <1>;
0126 #size-cells = <1>;
0127 ranges = <0 7 0 0x20000>;
0128
0129 v2m_sysreg: sysreg@0 {
0130 compatible = "arm,vexpress-sysreg";
0131 reg = <0x00000 0x1000>;
0132 #address-cells = <1>;
0133 #size-cells = <1>;
0134 ranges = <0 0 0x1000>;
0135
0136 v2m_led_gpios: gpio@8 {
0137 compatible = "arm,vexpress-sysreg,sys_led";
0138 reg = <0x008 4>;
0139 gpio-controller;
0140 #gpio-cells = <2>;
0141 };
0142
0143 v2m_mmc_gpios: gpio@48 {
0144 compatible = "arm,vexpress-sysreg,sys_mci";
0145 reg = <0x048 4>;
0146 gpio-controller;
0147 #gpio-cells = <2>;
0148 };
0149
0150 v2m_flash_gpios: gpio@4c {
0151 compatible = "arm,vexpress-sysreg,sys_flash";
0152 reg = <0x04c 4>;
0153 gpio-controller;
0154 #gpio-cells = <2>;
0155 };
0156 };
0157
0158 v2m_sysctl: sysctl@1000 {
0159 compatible = "arm,sp810", "arm,primecell";
0160 reg = <0x01000 0x1000>;
0161 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
0162 clock-names = "refclk", "timclk", "apb_pclk";
0163 #clock-cells = <1>;
0164 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
0165 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
0166 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
0167 };
0168
0169 /* PCI-E I2C bus */
0170 v2m_i2c_pcie: i2c@2000 {
0171 compatible = "arm,versatile-i2c";
0172 reg = <0x02000 0x1000>;
0173
0174 #address-cells = <1>;
0175 #size-cells = <0>;
0176
0177 pcie-switch@60 {
0178 compatible = "idt,89hpes32h8";
0179 reg = <0x60>;
0180 };
0181 };
0182
0183 aaci@4000 {
0184 compatible = "arm,pl041", "arm,primecell";
0185 reg = <0x04000 0x1000>;
0186 interrupts = <11>;
0187 clocks = <&smbclk>;
0188 clock-names = "apb_pclk";
0189 };
0190
0191 mmci@5000 {
0192 compatible = "arm,pl180", "arm,primecell";
0193 reg = <0x05000 0x1000>;
0194 interrupts = <9>, <10>;
0195 cd-gpios = <&v2m_mmc_gpios 0 0>;
0196 wp-gpios = <&v2m_mmc_gpios 1 0>;
0197 max-frequency = <12000000>;
0198 vmmc-supply = <&v2m_fixed_3v3>;
0199 clocks = <&v2m_clk24mhz>, <&smbclk>;
0200 clock-names = "mclk", "apb_pclk";
0201 };
0202
0203 kmi@6000 {
0204 compatible = "arm,pl050", "arm,primecell";
0205 reg = <0x06000 0x1000>;
0206 interrupts = <12>;
0207 clocks = <&v2m_clk24mhz>, <&smbclk>;
0208 clock-names = "KMIREFCLK", "apb_pclk";
0209 };
0210
0211 kmi@7000 {
0212 compatible = "arm,pl050", "arm,primecell";
0213 reg = <0x07000 0x1000>;
0214 interrupts = <13>;
0215 clocks = <&v2m_clk24mhz>, <&smbclk>;
0216 clock-names = "KMIREFCLK", "apb_pclk";
0217 };
0218
0219 v2m_serial0: uart@9000 {
0220 compatible = "arm,pl011", "arm,primecell";
0221 reg = <0x09000 0x1000>;
0222 interrupts = <5>;
0223 clocks = <&v2m_oscclk2>, <&smbclk>;
0224 clock-names = "uartclk", "apb_pclk";
0225 };
0226
0227 v2m_serial1: uart@a000 {
0228 compatible = "arm,pl011", "arm,primecell";
0229 reg = <0x0a000 0x1000>;
0230 interrupts = <6>;
0231 clocks = <&v2m_oscclk2>, <&smbclk>;
0232 clock-names = "uartclk", "apb_pclk";
0233 };
0234
0235 v2m_serial2: uart@b000 {
0236 compatible = "arm,pl011", "arm,primecell";
0237 reg = <0x0b000 0x1000>;
0238 interrupts = <7>;
0239 clocks = <&v2m_oscclk2>, <&smbclk>;
0240 clock-names = "uartclk", "apb_pclk";
0241 };
0242
0243 v2m_serial3: uart@c000 {
0244 compatible = "arm,pl011", "arm,primecell";
0245 reg = <0x0c000 0x1000>;
0246 interrupts = <8>;
0247 clocks = <&v2m_oscclk2>, <&smbclk>;
0248 clock-names = "uartclk", "apb_pclk";
0249 };
0250
0251 wdt@f000 {
0252 compatible = "arm,sp805", "arm,primecell";
0253 reg = <0x0f000 0x1000>;
0254 interrupts = <0>;
0255 clocks = <&v2m_refclk32khz>, <&smbclk>;
0256 clock-names = "wdog_clk", "apb_pclk";
0257 };
0258
0259 v2m_timer01: timer@11000 {
0260 compatible = "arm,sp804", "arm,primecell";
0261 reg = <0x11000 0x1000>;
0262 interrupts = <2>;
0263 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
0264 clock-names = "timclken1", "timclken2", "apb_pclk";
0265 };
0266
0267 v2m_timer23: timer@12000 {
0268 compatible = "arm,sp804", "arm,primecell";
0269 reg = <0x12000 0x1000>;
0270 interrupts = <3>;
0271 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
0272 clock-names = "timclken1", "timclken2", "apb_pclk";
0273 };
0274
0275 /* DVI I2C bus */
0276 v2m_i2c_dvi: i2c@16000 {
0277 compatible = "arm,versatile-i2c";
0278 reg = <0x16000 0x1000>;
0279 #address-cells = <1>;
0280 #size-cells = <0>;
0281
0282 dvi-transmitter@39 {
0283 compatible = "sil,sii9022-tpi", "sil,sii9022";
0284 reg = <0x39>;
0285
0286 ports {
0287 #address-cells = <1>;
0288 #size-cells = <0>;
0289
0290 /*
0291 * Both the core tile and the motherboard routes their output
0292 * pads to this transmitter. The motherboard system controller
0293 * can select one of them as input using a mux register in
0294 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
0295 * the only platform with this specific set-up.
0296 */
0297 port@0 {
0298 reg = <0>;
0299 dvi_bridge_in_ct: endpoint {
0300 remote-endpoint = <&clcd_pads_ct>;
0301 };
0302 };
0303 port@1 {
0304 reg = <1>;
0305 dvi_bridge_in_mb: endpoint {
0306 remote-endpoint = <&clcd_pads_mb>;
0307 };
0308 };
0309 };
0310 };
0311
0312 dvi-transmitter@60 {
0313 compatible = "sil,sii9022-cpi", "sil,sii9022";
0314 reg = <0x60>;
0315 };
0316 };
0317
0318 rtc@17000 {
0319 compatible = "arm,pl031", "arm,primecell";
0320 reg = <0x17000 0x1000>;
0321 interrupts = <4>;
0322 clocks = <&smbclk>;
0323 clock-names = "apb_pclk";
0324 };
0325
0326 compact-flash@1a000 {
0327 compatible = "arm,vexpress-cf", "ata-generic";
0328 reg = <0x1a000 0x100
0329 0x1a100 0xf00>;
0330 reg-shift = <2>;
0331 };
0332
0333
0334 clcd@1f000 {
0335 compatible = "arm,pl111", "arm,primecell";
0336 reg = <0x1f000 0x1000>;
0337 interrupt-names = "combined";
0338 interrupts = <14>;
0339 clocks = <&v2m_oscclk1>, <&smbclk>;
0340 clock-names = "clcdclk", "apb_pclk";
0341 /* 800x600 16bpp @36MHz works fine */
0342 max-memory-bandwidth = <54000000>;
0343 memory-region = <&vram>;
0344
0345 port {
0346 clcd_pads_mb: endpoint {
0347 remote-endpoint = <&dvi_bridge_in_mb>;
0348 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0349 };
0350 };
0351 };
0352 };
0353
0354 v2m_fixed_3v3: fixed-regulator-0 {
0355 compatible = "regulator-fixed";
0356 regulator-name = "3V3";
0357 regulator-min-microvolt = <3300000>;
0358 regulator-max-microvolt = <3300000>;
0359 regulator-always-on;
0360 };
0361
0362 v2m_clk24mhz: clk24mhz {
0363 compatible = "fixed-clock";
0364 #clock-cells = <0>;
0365 clock-frequency = <24000000>;
0366 clock-output-names = "v2m:clk24mhz";
0367 };
0368
0369 v2m_refclk1mhz: refclk1mhz {
0370 compatible = "fixed-clock";
0371 #clock-cells = <0>;
0372 clock-frequency = <1000000>;
0373 clock-output-names = "v2m:refclk1mhz";
0374 };
0375
0376 v2m_refclk32khz: refclk32khz {
0377 compatible = "fixed-clock";
0378 #clock-cells = <0>;
0379 clock-frequency = <32768>;
0380 clock-output-names = "v2m:refclk32khz";
0381 };
0382
0383 leds {
0384 compatible = "gpio-leds";
0385
0386 user1 {
0387 label = "v2m:green:user1";
0388 gpios = <&v2m_led_gpios 0 0>;
0389 linux,default-trigger = "heartbeat";
0390 };
0391
0392 user2 {
0393 label = "v2m:green:user2";
0394 gpios = <&v2m_led_gpios 1 0>;
0395 linux,default-trigger = "mmc0";
0396 };
0397
0398 user3 {
0399 label = "v2m:green:user3";
0400 gpios = <&v2m_led_gpios 2 0>;
0401 linux,default-trigger = "cpu0";
0402 };
0403
0404 user4 {
0405 label = "v2m:green:user4";
0406 gpios = <&v2m_led_gpios 3 0>;
0407 linux,default-trigger = "cpu1";
0408 };
0409
0410 user5 {
0411 label = "v2m:green:user5";
0412 gpios = <&v2m_led_gpios 4 0>;
0413 linux,default-trigger = "cpu2";
0414 };
0415
0416 user6 {
0417 label = "v2m:green:user6";
0418 gpios = <&v2m_led_gpios 5 0>;
0419 linux,default-trigger = "cpu3";
0420 };
0421
0422 user7 {
0423 label = "v2m:green:user7";
0424 gpios = <&v2m_led_gpios 6 0>;
0425 linux,default-trigger = "cpu4";
0426 };
0427
0428 user8 {
0429 label = "v2m:green:user8";
0430 gpios = <&v2m_led_gpios 7 0>;
0431 linux,default-trigger = "cpu5";
0432 };
0433 };
0434
0435 mcc {
0436 compatible = "arm,vexpress,config-bus";
0437 arm,vexpress,config-bridge = <&v2m_sysreg>;
0438
0439 oscclk0 {
0440 /* MCC static memory clock */
0441 compatible = "arm,vexpress-osc";
0442 arm,vexpress-sysreg,func = <1 0>;
0443 freq-range = <25000000 60000000>;
0444 #clock-cells = <0>;
0445 clock-output-names = "v2m:oscclk0";
0446 };
0447
0448 v2m_oscclk1: oscclk1 {
0449 /* CLCD clock */
0450 compatible = "arm,vexpress-osc";
0451 arm,vexpress-sysreg,func = <1 1>;
0452 freq-range = <23750000 65000000>;
0453 #clock-cells = <0>;
0454 clock-output-names = "v2m:oscclk1";
0455 };
0456
0457 v2m_oscclk2: oscclk2 {
0458 /* IO FPGA peripheral clock */
0459 compatible = "arm,vexpress-osc";
0460 arm,vexpress-sysreg,func = <1 2>;
0461 freq-range = <24000000 24000000>;
0462 #clock-cells = <0>;
0463 clock-output-names = "v2m:oscclk2";
0464 };
0465
0466 volt-vio {
0467 /* Logic level voltage */
0468 compatible = "arm,vexpress-volt";
0469 arm,vexpress-sysreg,func = <2 0>;
0470 regulator-name = "VIO";
0471 regulator-always-on;
0472 label = "VIO";
0473 };
0474
0475 temp-mcc {
0476 /* MCC internal operating temperature */
0477 compatible = "arm,vexpress-temp";
0478 arm,vexpress-sysreg,func = <4 0>;
0479 label = "MCC";
0480 };
0481
0482 reset {
0483 compatible = "arm,vexpress-reset";
0484 arm,vexpress-sysreg,func = <5 0>;
0485 };
0486
0487 muxfpga {
0488 compatible = "arm,vexpress-muxfpga";
0489 arm,vexpress-sysreg,func = <7 0>;
0490 };
0491
0492 shutdown {
0493 compatible = "arm,vexpress-shutdown";
0494 arm,vexpress-sysreg,func = <8 0>;
0495 };
0496
0497 reboot {
0498 compatible = "arm,vexpress-reboot";
0499 arm,vexpress-sysreg,func = <9 0>;
0500 };
0501
0502 dvimode {
0503 compatible = "arm,vexpress-dvimode";
0504 arm,vexpress-sysreg,func = <11 0>;
0505 };
0506 };
0507 };
0508 };
0509 };
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