0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 / {
0005 model = "ARM Versatile AB";
0006 compatible = "arm,versatile-ab";
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009 interrupt-parent = <&vic>;
0010
0011 aliases {
0012 serial0 = &uart0;
0013 serial1 = &uart1;
0014 serial2 = &uart2;
0015 i2c0 = &i2c0;
0016 };
0017
0018 chosen {
0019 stdout-path = &uart0;
0020 };
0021
0022 memory {
0023 device_type = "memory";
0024 reg = <0x0 0x08000000>;
0025 };
0026
0027 xtal24mhz: xtal24mhz@24M {
0028 #clock-cells = <0>;
0029 compatible = "fixed-clock";
0030 clock-frequency = <24000000>;
0031 };
0032
0033 bridge {
0034 compatible = "ti,ths8134b", "ti,ths8134";
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037
0038 ports {
0039 #address-cells = <1>;
0040 #size-cells = <0>;
0041
0042 port@0 {
0043 reg = <0>;
0044
0045 vga_bridge_in: endpoint {
0046 remote-endpoint = <&clcd_pads_vga_dac>;
0047 };
0048 };
0049
0050 port@1 {
0051 reg = <1>;
0052
0053 vga_bridge_out: endpoint {
0054 remote-endpoint = <&vga_con_in>;
0055 };
0056 };
0057 };
0058 };
0059
0060 vga {
0061 compatible = "vga-connector";
0062
0063 port {
0064 vga_con_in: endpoint {
0065 remote-endpoint = <&vga_bridge_out>;
0066 };
0067 };
0068 };
0069
0070 core-module@10000000 {
0071 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
0072 reg = <0x10000000 0x200>;
0073 ranges = <0x0 0x10000000 0x200>;
0074 #address-cells = <1>;
0075 #size-cells = <1>;
0076
0077 led@8,0 {
0078 compatible = "register-bit-led";
0079 reg = <0x08 0x04>;
0080 offset = <0x08>;
0081 mask = <0x01>;
0082 label = "versatile:0";
0083 linux,default-trigger = "heartbeat";
0084 default-state = "on";
0085 };
0086 led@8,1 {
0087 compatible = "register-bit-led";
0088 reg = <0x08 0x04>;
0089 offset = <0x08>;
0090 mask = <0x02>;
0091 label = "versatile:1";
0092 linux,default-trigger = "mmc0";
0093 default-state = "off";
0094 };
0095 led@8,2 {
0096 compatible = "register-bit-led";
0097 reg = <0x08 0x04>;
0098 offset = <0x08>;
0099 mask = <0x04>;
0100 label = "versatile:2";
0101 linux,default-trigger = "cpu0";
0102 default-state = "off";
0103 };
0104 led@8,3 {
0105 compatible = "register-bit-led";
0106 reg = <0x08 0x04>;
0107 offset = <0x08>;
0108 mask = <0x08>;
0109 label = "versatile:3";
0110 default-state = "off";
0111 };
0112 led@8,4 {
0113 compatible = "register-bit-led";
0114 reg = <0x08 0x04>;
0115 offset = <0x08>;
0116 mask = <0x10>;
0117 label = "versatile:4";
0118 default-state = "off";
0119 };
0120 led@8,5 {
0121 compatible = "register-bit-led";
0122 reg = <0x08 0x04>;
0123 offset = <0x08>;
0124 mask = <0x20>;
0125 label = "versatile:5";
0126 default-state = "off";
0127 };
0128 led@8,6 {
0129 compatible = "register-bit-led";
0130 reg = <0x08 0x04>;
0131 offset = <0x08>;
0132 mask = <0x40>;
0133 label = "versatile:6";
0134 default-state = "off";
0135 };
0136 led@8,7 {
0137 compatible = "register-bit-led";
0138 reg = <0x08 0x04>;
0139 offset = <0x08>;
0140 mask = <0x80>;
0141 label = "versatile:7";
0142 default-state = "off";
0143 };
0144
0145 /* OSC1 on AB, OSC4 on PB */
0146 osc1: cm_aux_osc@24M {
0147 #clock-cells = <0>;
0148 compatible = "arm,versatile-cm-auxosc";
0149 clocks = <&xtal24mhz>;
0150 };
0151
0152 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
0153 timclk: timclk@1M {
0154 #clock-cells = <0>;
0155 compatible = "fixed-factor-clock";
0156 clock-div = <24>;
0157 clock-mult = <1>;
0158 clocks = <&xtal24mhz>;
0159 };
0160
0161 pclk: pclk@24M {
0162 #clock-cells = <0>;
0163 compatible = "fixed-factor-clock";
0164 clock-div = <1>;
0165 clock-mult = <1>;
0166 clocks = <&xtal24mhz>;
0167 };
0168 };
0169
0170 flash@34000000 {
0171 /* 64 MiB NOR flash in non-interleaved chips */
0172 compatible = "arm,versatile-flash", "cfi-flash";
0173 reg = <0x34000000 0x04000000>;
0174 bank-width = <4>;
0175 partitions {
0176 compatible = "arm,arm-firmware-suite";
0177 };
0178 };
0179
0180 i2c0: i2c@10002000 {
0181 #address-cells = <1>;
0182 #size-cells = <0>;
0183 compatible = "arm,versatile-i2c";
0184 reg = <0x10002000 0x1000>;
0185
0186 rtc@68 {
0187 compatible = "dallas,ds1338";
0188 reg = <0x68>;
0189 };
0190 };
0191
0192 net@10010000 {
0193 compatible = "smsc,lan91c111";
0194 reg = <0x10010000 0x10000>;
0195 interrupts = <25>;
0196 };
0197
0198 lcd@10008000 {
0199 compatible = "arm,versatile-lcd";
0200 reg = <0x10008000 0x1000>;
0201 };
0202
0203 amba {
0204 compatible = "simple-bus";
0205 #address-cells = <1>;
0206 #size-cells = <1>;
0207 ranges;
0208
0209 vic: interrupt-controller@10140000 {
0210 compatible = "arm,versatile-vic";
0211 interrupt-controller;
0212 #interrupt-cells = <1>;
0213 reg = <0x10140000 0x1000>;
0214 valid-mask = <0xffffffff>;
0215 };
0216
0217 sic: interrupt-controller@10003000 {
0218 compatible = "arm,versatile-sic";
0219 interrupt-controller;
0220 #interrupt-cells = <1>;
0221 reg = <0x10003000 0x1000>;
0222 interrupt-parent = <&vic>;
0223 interrupts = <31>; /* Cascaded to vic */
0224 clear-mask = <0xffffffff>;
0225 /*
0226 * Valid interrupt lines mask according to
0227 * table 4-36 page 4-50 of ARM DUI 0225D
0228 */
0229 valid-mask = <0x0760031b>;
0230 };
0231
0232 dma@10130000 {
0233 compatible = "arm,pl081", "arm,primecell";
0234 reg = <0x10130000 0x1000>;
0235 interrupts = <17>;
0236 clocks = <&pclk>;
0237 clock-names = "apb_pclk";
0238 };
0239
0240 uart0: uart@101f1000 {
0241 compatible = "arm,pl011", "arm,primecell";
0242 reg = <0x101f1000 0x1000>;
0243 interrupts = <12>;
0244 clocks = <&xtal24mhz>, <&pclk>;
0245 clock-names = "uartclk", "apb_pclk";
0246 };
0247
0248 uart1: uart@101f2000 {
0249 compatible = "arm,pl011", "arm,primecell";
0250 reg = <0x101f2000 0x1000>;
0251 interrupts = <13>;
0252 clocks = <&xtal24mhz>, <&pclk>;
0253 clock-names = "uartclk", "apb_pclk";
0254 };
0255
0256 uart2: uart@101f3000 {
0257 compatible = "arm,pl011", "arm,primecell";
0258 reg = <0x101f3000 0x1000>;
0259 interrupts = <14>;
0260 clocks = <&xtal24mhz>, <&pclk>;
0261 clock-names = "uartclk", "apb_pclk";
0262 };
0263
0264 smc@10100000 {
0265 compatible = "arm,primecell";
0266 reg = <0x10100000 0x1000>;
0267 clocks = <&pclk>;
0268 clock-names = "apb_pclk";
0269 };
0270
0271 mpmc@10110000 {
0272 compatible = "arm,primecell";
0273 reg = <0x10110000 0x1000>;
0274 clocks = <&pclk>;
0275 clock-names = "apb_pclk";
0276 };
0277
0278 display@10120000 {
0279 compatible = "arm,pl110", "arm,primecell";
0280 reg = <0x10120000 0x1000>;
0281 interrupts = <16>;
0282 clocks = <&osc1>, <&pclk>;
0283 clock-names = "clcdclk", "apb_pclk";
0284 /* 800x600 16bpp @ 36MHz works fine */
0285 max-memory-bandwidth = <54000000>;
0286
0287 /*
0288 * This port is routed through a PLD (Programmable
0289 * Logic Device) that routes the output from the CLCD
0290 * (after transformations) to the VGA DAC and also an
0291 * external panel connector. The PLD is essential for
0292 * supporting RGB565/BGR565.
0293 *
0294 * The signals from the port thus reaches two endpoints.
0295 * The PLD is managed through a few special bits in the
0296 * FPGA "sysreg".
0297 *
0298 * This arrangement can be clearly seen in
0299 * ARM DUI 0225D, page 3-41, figure 3-19.
0300 */
0301 port@0 {
0302 #address-cells = <1>;
0303 #size-cells = <0>;
0304
0305 clcd_pads_panel: endpoint@0 {
0306 reg = <0>;
0307 remote-endpoint = <&panel_in>;
0308 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0309 };
0310 clcd_pads_vga_dac: endpoint@1 {
0311 reg = <1>;
0312 remote-endpoint = <&vga_bridge_in>;
0313 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0314 };
0315 };
0316 };
0317
0318 sctl@101e0000 {
0319 compatible = "arm,primecell";
0320 reg = <0x101e0000 0x1000>;
0321 clocks = <&pclk>;
0322 clock-names = "apb_pclk";
0323 };
0324
0325 watchdog@101e1000 {
0326 compatible = "arm,primecell";
0327 reg = <0x101e1000 0x1000>;
0328 interrupts = <0>;
0329 clocks = <&pclk>;
0330 clock-names = "apb_pclk";
0331 };
0332
0333 timer@101e2000 {
0334 compatible = "arm,sp804", "arm,primecell";
0335 reg = <0x101e2000 0x1000>;
0336 interrupts = <4>;
0337 clocks = <&timclk>, <&timclk>, <&pclk>;
0338 clock-names = "timer0", "timer1", "apb_pclk";
0339 };
0340
0341 timer@101e3000 {
0342 compatible = "arm,sp804", "arm,primecell";
0343 reg = <0x101e3000 0x1000>;
0344 interrupts = <5>;
0345 clocks = <&timclk>, <&timclk>, <&pclk>;
0346 clock-names = "timer0", "timer1", "apb_pclk";
0347 };
0348
0349 gpio0: gpio@101e4000 {
0350 compatible = "arm,pl061", "arm,primecell";
0351 reg = <0x101e4000 0x1000>;
0352 gpio-controller;
0353 interrupts = <6>;
0354 #gpio-cells = <2>;
0355 interrupt-controller;
0356 #interrupt-cells = <2>;
0357 clocks = <&pclk>;
0358 clock-names = "apb_pclk";
0359 };
0360
0361 gpio1: gpio@101e5000 {
0362 compatible = "arm,pl061", "arm,primecell";
0363 reg = <0x101e5000 0x1000>;
0364 interrupts = <7>;
0365 gpio-controller;
0366 #gpio-cells = <2>;
0367 interrupt-controller;
0368 #interrupt-cells = <2>;
0369 clocks = <&pclk>;
0370 clock-names = "apb_pclk";
0371 };
0372
0373 rtc@101e8000 {
0374 compatible = "arm,pl030", "arm,primecell";
0375 reg = <0x101e8000 0x1000>;
0376 interrupts = <10>;
0377 clocks = <&pclk>;
0378 clock-names = "apb_pclk";
0379 };
0380
0381 sci@101f0000 {
0382 compatible = "arm,primecell";
0383 reg = <0x101f0000 0x1000>;
0384 interrupts = <15>;
0385 clocks = <&pclk>;
0386 clock-names = "apb_pclk";
0387 };
0388
0389 spi@101f4000 {
0390 compatible = "arm,pl022", "arm,primecell";
0391 reg = <0x101f4000 0x1000>;
0392 interrupts = <11>;
0393 clocks = <&xtal24mhz>, <&pclk>;
0394 clock-names = "sspclk", "apb_pclk";
0395 };
0396
0397 fpga {
0398 compatible = "arm,versatile-fpga", "simple-bus";
0399 #address-cells = <1>;
0400 #size-cells = <1>;
0401 ranges = <0 0x10000000 0x10000>;
0402
0403 sysreg@0 {
0404 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
0405 reg = <0x00000 0x1000>;
0406
0407 panel: display@0 {
0408 compatible = "arm,versatile-tft-panel";
0409
0410 port {
0411 panel_in: endpoint {
0412 remote-endpoint = <&clcd_pads_panel>;
0413 };
0414 };
0415 };
0416 };
0417
0418 aaci@4000 {
0419 compatible = "arm,primecell";
0420 reg = <0x4000 0x1000>;
0421 interrupts = <24>;
0422 clocks = <&pclk>;
0423 clock-names = "apb_pclk";
0424 };
0425 mmc@5000 {
0426 compatible = "arm,pl180", "arm,primecell";
0427 reg = <0x5000 0x1000>;
0428 interrupts-extended = <&vic 22 &sic 1>;
0429 clocks = <&xtal24mhz>, <&pclk>;
0430 clock-names = "mclk", "apb_pclk";
0431 };
0432 kmi@6000 {
0433 compatible = "arm,pl050", "arm,primecell";
0434 reg = <0x6000 0x1000>;
0435 interrupt-parent = <&sic>;
0436 interrupts = <3>;
0437 clocks = <&xtal24mhz>, <&pclk>;
0438 clock-names = "KMIREFCLK", "apb_pclk";
0439 };
0440 kmi@7000 {
0441 compatible = "arm,pl050", "arm,primecell";
0442 reg = <0x7000 0x1000>;
0443 interrupt-parent = <&sic>;
0444 interrupts = <4>;
0445 clocks = <&xtal24mhz>, <&pclk>;
0446 clock-names = "KMIREFCLK", "apb_pclk";
0447 };
0448 };
0449 };
0450 };
