0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Device Tree Source for UniPhier sLD8 SoC
0004 //
0005 // Copyright (C) 2015-2016 Socionext Inc.
0006 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0007
0008 #include <dt-bindings/gpio/uniphier-gpio.h>
0009
0010 / {
0011 compatible = "socionext,uniphier-sld8";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu@0 {
0020 device_type = "cpu";
0021 compatible = "arm,cortex-a9";
0022 reg = <0>;
0023 enable-method = "psci";
0024 next-level-cache = <&l2>;
0025 };
0026 };
0027
0028 psci {
0029 compatible = "arm,psci-0.2";
0030 method = "smc";
0031 };
0032
0033 clocks {
0034 refclk: ref {
0035 compatible = "fixed-clock";
0036 #clock-cells = <0>;
0037 clock-frequency = <25000000>;
0038 };
0039
0040 arm_timer_clk: arm-timer {
0041 #clock-cells = <0>;
0042 compatible = "fixed-clock";
0043 clock-frequency = <50000000>;
0044 };
0045 };
0046
0047 soc {
0048 compatible = "simple-bus";
0049 #address-cells = <1>;
0050 #size-cells = <1>;
0051 ranges;
0052 interrupt-parent = <&intc>;
0053
0054 l2: cache-controller@500c0000 {
0055 compatible = "socionext,uniphier-system-cache";
0056 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
0057 <0x506c0000 0x400>;
0058 interrupts = <0 174 4>, <0 175 4>;
0059 cache-unified;
0060 cache-size = <(256 * 1024)>;
0061 cache-sets = <256>;
0062 cache-line-size = <128>;
0063 cache-level = <2>;
0064 };
0065
0066 spi: spi@54006000 {
0067 compatible = "socionext,uniphier-scssi";
0068 status = "disabled";
0069 reg = <0x54006000 0x100>;
0070 #address-cells = <1>;
0071 #size-cells = <0>;
0072 interrupts = <0 39 4>;
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&pinctrl_spi0>;
0075 clocks = <&peri_clk 11>;
0076 resets = <&peri_rst 11>;
0077 };
0078
0079 serial0: serial@54006800 {
0080 compatible = "socionext,uniphier-uart";
0081 status = "disabled";
0082 reg = <0x54006800 0x40>;
0083 interrupts = <0 33 4>;
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_uart0>;
0086 clocks = <&peri_clk 0>;
0087 resets = <&peri_rst 0>;
0088 };
0089
0090 serial1: serial@54006900 {
0091 compatible = "socionext,uniphier-uart";
0092 status = "disabled";
0093 reg = <0x54006900 0x40>;
0094 interrupts = <0 35 4>;
0095 pinctrl-names = "default";
0096 pinctrl-0 = <&pinctrl_uart1>;
0097 clocks = <&peri_clk 1>;
0098 resets = <&peri_rst 1>;
0099 };
0100
0101 serial2: serial@54006a00 {
0102 compatible = "socionext,uniphier-uart";
0103 status = "disabled";
0104 reg = <0x54006a00 0x40>;
0105 interrupts = <0 37 4>;
0106 pinctrl-names = "default";
0107 pinctrl-0 = <&pinctrl_uart2>;
0108 clocks = <&peri_clk 2>;
0109 resets = <&peri_rst 2>;
0110 };
0111
0112 serial3: serial@54006b00 {
0113 compatible = "socionext,uniphier-uart";
0114 status = "disabled";
0115 reg = <0x54006b00 0x40>;
0116 interrupts = <0 29 4>;
0117 pinctrl-names = "default";
0118 pinctrl-0 = <&pinctrl_uart3>;
0119 clocks = <&peri_clk 3>;
0120 resets = <&peri_rst 3>;
0121 };
0122
0123 gpio: gpio@55000000 {
0124 compatible = "socionext,uniphier-gpio";
0125 reg = <0x55000000 0x200>;
0126 interrupt-parent = <&aidet>;
0127 interrupt-controller;
0128 #interrupt-cells = <2>;
0129 gpio-controller;
0130 #gpio-cells = <2>;
0131 gpio-ranges = <&pinctrl 0 0 0>,
0132 <&pinctrl 104 0 0>,
0133 <&pinctrl 112 0 0>;
0134 gpio-ranges-group-names = "gpio_range0",
0135 "gpio_range1",
0136 "gpio_range2";
0137 ngpios = <136>;
0138 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
0139 };
0140
0141 i2c0: i2c@58400000 {
0142 compatible = "socionext,uniphier-i2c";
0143 status = "disabled";
0144 reg = <0x58400000 0x40>;
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 interrupts = <0 41 1>;
0148 pinctrl-names = "default";
0149 pinctrl-0 = <&pinctrl_i2c0>;
0150 clocks = <&peri_clk 4>;
0151 resets = <&peri_rst 4>;
0152 clock-frequency = <100000>;
0153 };
0154
0155 i2c1: i2c@58480000 {
0156 compatible = "socionext,uniphier-i2c";
0157 status = "disabled";
0158 reg = <0x58480000 0x40>;
0159 #address-cells = <1>;
0160 #size-cells = <0>;
0161 interrupts = <0 42 1>;
0162 pinctrl-names = "default";
0163 pinctrl-0 = <&pinctrl_i2c1>;
0164 clocks = <&peri_clk 5>;
0165 resets = <&peri_rst 5>;
0166 clock-frequency = <100000>;
0167 };
0168
0169 /* chip-internal connection for DMD */
0170 i2c2: i2c@58500000 {
0171 compatible = "socionext,uniphier-i2c";
0172 reg = <0x58500000 0x40>;
0173 #address-cells = <1>;
0174 #size-cells = <0>;
0175 interrupts = <0 43 1>;
0176 pinctrl-names = "default";
0177 pinctrl-0 = <&pinctrl_i2c2>;
0178 clocks = <&peri_clk 6>;
0179 resets = <&peri_rst 6>;
0180 clock-frequency = <400000>;
0181 };
0182
0183 i2c3: i2c@58580000 {
0184 compatible = "socionext,uniphier-i2c";
0185 status = "disabled";
0186 reg = <0x58580000 0x40>;
0187 #address-cells = <1>;
0188 #size-cells = <0>;
0189 interrupts = <0 44 1>;
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&pinctrl_i2c3>;
0192 clocks = <&peri_clk 7>;
0193 resets = <&peri_rst 7>;
0194 clock-frequency = <100000>;
0195 };
0196
0197 system_bus: system-bus@58c00000 {
0198 compatible = "socionext,uniphier-system-bus";
0199 status = "disabled";
0200 reg = <0x58c00000 0x400>;
0201 #address-cells = <2>;
0202 #size-cells = <1>;
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&pinctrl_system_bus>;
0205 };
0206
0207 smpctrl@59801000 {
0208 compatible = "socionext,uniphier-smpctrl";
0209 reg = <0x59801000 0x400>;
0210 };
0211
0212 mioctrl@59810000 {
0213 compatible = "socionext,uniphier-sld8-mioctrl",
0214 "simple-mfd", "syscon";
0215 reg = <0x59810000 0x800>;
0216
0217 mio_clk: clock {
0218 compatible = "socionext,uniphier-sld8-mio-clock";
0219 #clock-cells = <1>;
0220 };
0221
0222 mio_rst: reset {
0223 compatible = "socionext,uniphier-sld8-mio-reset";
0224 #reset-cells = <1>;
0225 };
0226 };
0227
0228 perictrl@59820000 {
0229 compatible = "socionext,uniphier-sld8-perictrl",
0230 "simple-mfd", "syscon";
0231 reg = <0x59820000 0x200>;
0232
0233 peri_clk: clock {
0234 compatible = "socionext,uniphier-sld8-peri-clock";
0235 #clock-cells = <1>;
0236 };
0237
0238 peri_rst: reset {
0239 compatible = "socionext,uniphier-sld8-peri-reset";
0240 #reset-cells = <1>;
0241 };
0242 };
0243
0244 dmac: dma-controller@5a000000 {
0245 compatible = "socionext,uniphier-mio-dmac";
0246 reg = <0x5a000000 0x1000>;
0247 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
0248 <0 71 4>, <0 72 4>, <0 73 4>;
0249 clocks = <&mio_clk 7>;
0250 resets = <&mio_rst 7>;
0251 #dma-cells = <1>;
0252 };
0253
0254 sd: mmc@5a400000 {
0255 compatible = "socionext,uniphier-sd-v2.91";
0256 status = "disabled";
0257 reg = <0x5a400000 0x200>;
0258 interrupts = <0 76 4>;
0259 pinctrl-names = "default", "uhs";
0260 pinctrl-0 = <&pinctrl_sd>;
0261 pinctrl-1 = <&pinctrl_sd_uhs>;
0262 clocks = <&mio_clk 0>;
0263 reset-names = "host", "bridge";
0264 resets = <&mio_rst 0>, <&mio_rst 3>;
0265 dma-names = "rx-tx";
0266 dmas = <&dmac 4>;
0267 bus-width = <4>;
0268 cap-sd-highspeed;
0269 sd-uhs-sdr12;
0270 sd-uhs-sdr25;
0271 sd-uhs-sdr50;
0272 };
0273
0274 emmc: mmc@5a500000 {
0275 compatible = "socionext,uniphier-sd-v2.91";
0276 status = "disabled";
0277 reg = <0x5a500000 0x200>;
0278 interrupts = <0 78 4>;
0279 pinctrl-names = "default";
0280 pinctrl-0 = <&pinctrl_emmc>;
0281 clocks = <&mio_clk 1>;
0282 reset-names = "host", "bridge", "hw";
0283 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
0284 dma-names = "rx-tx";
0285 dmas = <&dmac 6>;
0286 bus-width = <8>;
0287 cap-mmc-highspeed;
0288 cap-mmc-hw-reset;
0289 non-removable;
0290 };
0291
0292 usb0: usb@5a800100 {
0293 compatible = "socionext,uniphier-ehci", "generic-ehci";
0294 status = "disabled";
0295 reg = <0x5a800100 0x100>;
0296 interrupts = <0 80 4>;
0297 pinctrl-names = "default";
0298 pinctrl-0 = <&pinctrl_usb0>;
0299 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
0300 <&mio_clk 12>;
0301 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
0302 <&mio_rst 12>;
0303 has-transaction-translator;
0304 };
0305
0306 usb1: usb@5a810100 {
0307 compatible = "socionext,uniphier-ehci", "generic-ehci";
0308 status = "disabled";
0309 reg = <0x5a810100 0x100>;
0310 interrupts = <0 81 4>;
0311 pinctrl-names = "default";
0312 pinctrl-0 = <&pinctrl_usb1>;
0313 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
0314 <&mio_clk 13>;
0315 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
0316 <&mio_rst 13>;
0317 has-transaction-translator;
0318 };
0319
0320 usb2: usb@5a820100 {
0321 compatible = "socionext,uniphier-ehci", "generic-ehci";
0322 status = "disabled";
0323 reg = <0x5a820100 0x100>;
0324 interrupts = <0 82 4>;
0325 pinctrl-names = "default";
0326 pinctrl-0 = <&pinctrl_usb2>;
0327 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
0328 <&mio_clk 14>;
0329 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
0330 <&mio_rst 14>;
0331 has-transaction-translator;
0332 };
0333
0334 soc-glue@5f800000 {
0335 compatible = "socionext,uniphier-sld8-soc-glue",
0336 "simple-mfd", "syscon";
0337 reg = <0x5f800000 0x2000>;
0338
0339 pinctrl: pinctrl {
0340 compatible = "socionext,uniphier-sld8-pinctrl";
0341 };
0342 };
0343
0344 soc-glue@5f900000 {
0345 compatible = "socionext,uniphier-sld8-soc-glue-debug",
0346 "simple-mfd";
0347 #address-cells = <1>;
0348 #size-cells = <1>;
0349 ranges = <0 0x5f900000 0x2000>;
0350
0351 efuse@100 {
0352 compatible = "socionext,uniphier-efuse";
0353 reg = <0x100 0x28>;
0354 };
0355
0356 efuse@200 {
0357 compatible = "socionext,uniphier-efuse";
0358 reg = <0x200 0x14>;
0359 };
0360 };
0361
0362 timer@60000200 {
0363 compatible = "arm,cortex-a9-global-timer";
0364 reg = <0x60000200 0x20>;
0365 interrupts = <1 11 0x104>;
0366 clocks = <&arm_timer_clk>;
0367 };
0368
0369 timer@60000600 {
0370 compatible = "arm,cortex-a9-twd-timer";
0371 reg = <0x60000600 0x20>;
0372 interrupts = <1 13 0x104>;
0373 clocks = <&arm_timer_clk>;
0374 };
0375
0376 intc: interrupt-controller@60001000 {
0377 compatible = "arm,cortex-a9-gic";
0378 reg = <0x60001000 0x1000>,
0379 <0x60000100 0x100>;
0380 #interrupt-cells = <3>;
0381 interrupt-controller;
0382 };
0383
0384 aidet: interrupt-controller@61830000 {
0385 compatible = "socionext,uniphier-sld8-aidet";
0386 reg = <0x61830000 0x200>;
0387 interrupt-controller;
0388 #interrupt-cells = <2>;
0389 };
0390
0391 sysctrl@61840000 {
0392 compatible = "socionext,uniphier-sld8-sysctrl",
0393 "simple-mfd", "syscon";
0394 reg = <0x61840000 0x10000>;
0395
0396 sys_clk: clock {
0397 compatible = "socionext,uniphier-sld8-clock";
0398 #clock-cells = <1>;
0399 };
0400
0401 sys_rst: reset {
0402 compatible = "socionext,uniphier-sld8-reset";
0403 #reset-cells = <1>;
0404 };
0405 };
0406
0407 nand: nand-controller@68000000 {
0408 compatible = "socionext,uniphier-denali-nand-v5a";
0409 status = "disabled";
0410 reg-names = "nand_data", "denali_reg";
0411 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
0412 #address-cells = <1>;
0413 #size-cells = <0>;
0414 interrupts = <0 65 4>;
0415 pinctrl-names = "default";
0416 pinctrl-0 = <&pinctrl_nand>;
0417 clock-names = "nand", "nand_x", "ecc";
0418 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
0419 reset-names = "nand", "reg";
0420 resets = <&sys_rst 2>, <&sys_rst 2>;
0421 };
0422 };
0423 };
0424
0425 #include "uniphier-pinctrl.dtsi"
