0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Device Tree Source for UniPhier PXs2 SoC
0004 //
0005 // Copyright (C) 2015-2016 Socionext Inc.
0006 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0007
0008 #include <dt-bindings/gpio/uniphier-gpio.h>
0009 #include <dt-bindings/thermal/thermal.h>
0010
0011 / {
0012 compatible = "socionext,uniphier-pxs2";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019
0020 cpu0: cpu@0 {
0021 device_type = "cpu";
0022 compatible = "arm,cortex-a9";
0023 reg = <0>;
0024 clocks = <&sys_clk 32>;
0025 enable-method = "psci";
0026 next-level-cache = <&l2>;
0027 operating-points-v2 = <&cpu_opp>;
0028 #cooling-cells = <2>;
0029 };
0030
0031 cpu1: cpu@1 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a9";
0034 reg = <1>;
0035 clocks = <&sys_clk 32>;
0036 enable-method = "psci";
0037 next-level-cache = <&l2>;
0038 operating-points-v2 = <&cpu_opp>;
0039 #cooling-cells = <2>;
0040 };
0041
0042 cpu2: cpu@2 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a9";
0045 reg = <2>;
0046 clocks = <&sys_clk 32>;
0047 enable-method = "psci";
0048 next-level-cache = <&l2>;
0049 operating-points-v2 = <&cpu_opp>;
0050 #cooling-cells = <2>;
0051 };
0052
0053 cpu3: cpu@3 {
0054 device_type = "cpu";
0055 compatible = "arm,cortex-a9";
0056 reg = <3>;
0057 clocks = <&sys_clk 32>;
0058 enable-method = "psci";
0059 next-level-cache = <&l2>;
0060 operating-points-v2 = <&cpu_opp>;
0061 #cooling-cells = <2>;
0062 };
0063 };
0064
0065 cpu_opp: opp-table {
0066 compatible = "operating-points-v2";
0067 opp-shared;
0068
0069 opp-100000000 {
0070 opp-hz = /bits/ 64 <100000000>;
0071 clock-latency-ns = <300>;
0072 };
0073 opp-150000000 {
0074 opp-hz = /bits/ 64 <150000000>;
0075 clock-latency-ns = <300>;
0076 };
0077 opp-200000000 {
0078 opp-hz = /bits/ 64 <200000000>;
0079 clock-latency-ns = <300>;
0080 };
0081 opp-300000000 {
0082 opp-hz = /bits/ 64 <300000000>;
0083 clock-latency-ns = <300>;
0084 };
0085 opp-400000000 {
0086 opp-hz = /bits/ 64 <400000000>;
0087 clock-latency-ns = <300>;
0088 };
0089 opp-600000000 {
0090 opp-hz = /bits/ 64 <600000000>;
0091 clock-latency-ns = <300>;
0092 };
0093 opp-800000000 {
0094 opp-hz = /bits/ 64 <800000000>;
0095 clock-latency-ns = <300>;
0096 };
0097 opp-1200000000 {
0098 opp-hz = /bits/ 64 <1200000000>;
0099 clock-latency-ns = <300>;
0100 };
0101 };
0102
0103 psci {
0104 compatible = "arm,psci-0.2";
0105 method = "smc";
0106 };
0107
0108 clocks {
0109 refclk: ref {
0110 compatible = "fixed-clock";
0111 #clock-cells = <0>;
0112 clock-frequency = <25000000>;
0113 };
0114
0115 arm_timer_clk: arm-timer {
0116 #clock-cells = <0>;
0117 compatible = "fixed-clock";
0118 clock-frequency = <50000000>;
0119 };
0120 };
0121
0122 thermal-zones {
0123 cpu-thermal {
0124 polling-delay-passive = <250>; /* 250ms */
0125 polling-delay = <1000>; /* 1000ms */
0126 thermal-sensors = <&pvtctl>;
0127
0128 trips {
0129 cpu_crit: cpu-crit {
0130 temperature = <95000>; /* 95C */
0131 hysteresis = <2000>;
0132 type = "critical";
0133 };
0134 cpu_alert: cpu-alert {
0135 temperature = <85000>; /* 85C */
0136 hysteresis = <2000>;
0137 type = "passive";
0138 };
0139 };
0140
0141 cooling-maps {
0142 map {
0143 trip = <&cpu_alert>;
0144 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0145 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0146 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0147 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0148 };
0149 };
0150 };
0151 };
0152
0153 soc {
0154 compatible = "simple-bus";
0155 #address-cells = <1>;
0156 #size-cells = <1>;
0157 ranges;
0158 interrupt-parent = <&intc>;
0159
0160 l2: cache-controller@500c0000 {
0161 compatible = "socionext,uniphier-system-cache";
0162 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
0163 <0x506c0000 0x400>;
0164 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
0165 cache-unified;
0166 cache-size = <(1280 * 1024)>;
0167 cache-sets = <512>;
0168 cache-line-size = <128>;
0169 cache-level = <2>;
0170 };
0171
0172 spi0: spi@54006000 {
0173 compatible = "socionext,uniphier-scssi";
0174 status = "disabled";
0175 reg = <0x54006000 0x100>;
0176 #address-cells = <1>;
0177 #size-cells = <0>;
0178 interrupts = <0 39 4>;
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_spi0>;
0181 clocks = <&peri_clk 11>;
0182 resets = <&peri_rst 11>;
0183 };
0184
0185 spi1: spi@54006100 {
0186 compatible = "socionext,uniphier-scssi";
0187 status = "disabled";
0188 reg = <0x54006100 0x100>;
0189 #address-cells = <1>;
0190 #size-cells = <0>;
0191 interrupts = <0 216 4>;
0192 pinctrl-names = "default";
0193 pinctrl-0 = <&pinctrl_spi1>;
0194 clocks = <&peri_clk 12>;
0195 resets = <&peri_rst 12>;
0196 };
0197
0198 serial0: serial@54006800 {
0199 compatible = "socionext,uniphier-uart";
0200 status = "disabled";
0201 reg = <0x54006800 0x40>;
0202 interrupts = <0 33 4>;
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&pinctrl_uart0>;
0205 clocks = <&peri_clk 0>;
0206 resets = <&peri_rst 0>;
0207 };
0208
0209 serial1: serial@54006900 {
0210 compatible = "socionext,uniphier-uart";
0211 status = "disabled";
0212 reg = <0x54006900 0x40>;
0213 interrupts = <0 35 4>;
0214 pinctrl-names = "default";
0215 pinctrl-0 = <&pinctrl_uart1>;
0216 clocks = <&peri_clk 1>;
0217 resets = <&peri_rst 1>;
0218 };
0219
0220 serial2: serial@54006a00 {
0221 compatible = "socionext,uniphier-uart";
0222 status = "disabled";
0223 reg = <0x54006a00 0x40>;
0224 interrupts = <0 37 4>;
0225 pinctrl-names = "default";
0226 pinctrl-0 = <&pinctrl_uart2>;
0227 clocks = <&peri_clk 2>;
0228 resets = <&peri_rst 2>;
0229 };
0230
0231 serial3: serial@54006b00 {
0232 compatible = "socionext,uniphier-uart";
0233 status = "disabled";
0234 reg = <0x54006b00 0x40>;
0235 interrupts = <0 177 4>;
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_uart3>;
0238 clocks = <&peri_clk 3>;
0239 resets = <&peri_rst 3>;
0240 };
0241
0242 gpio: gpio@55000000 {
0243 compatible = "socionext,uniphier-gpio";
0244 reg = <0x55000000 0x200>;
0245 interrupt-parent = <&aidet>;
0246 interrupt-controller;
0247 #interrupt-cells = <2>;
0248 gpio-controller;
0249 #gpio-cells = <2>;
0250 gpio-ranges = <&pinctrl 0 0 0>,
0251 <&pinctrl 96 0 0>;
0252 gpio-ranges-group-names = "gpio_range0",
0253 "gpio_range1";
0254 ngpios = <232>;
0255 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
0256 <21 217 3>;
0257 };
0258
0259 audio@56000000 {
0260 compatible = "socionext,uniphier-pxs2-aio";
0261 reg = <0x56000000 0x80000>;
0262 interrupts = <0 144 4>;
0263 pinctrl-names = "default";
0264 pinctrl-0 = <&pinctrl_ain1>,
0265 <&pinctrl_ain2>,
0266 <&pinctrl_ainiec1>,
0267 <&pinctrl_aout2>,
0268 <&pinctrl_aout3>,
0269 <&pinctrl_aoutiec1>,
0270 <&pinctrl_aoutiec2>;
0271 clock-names = "aio";
0272 clocks = <&sys_clk 40>;
0273 reset-names = "aio";
0274 resets = <&sys_rst 40>;
0275 #sound-dai-cells = <1>;
0276 socionext,syscon = <&soc_glue>;
0277
0278 i2s_port0: port@0 {
0279 i2s_hdmi: endpoint {
0280 };
0281 };
0282
0283 i2s_port1: port@1 {
0284 i2s_line: endpoint {
0285 };
0286 };
0287
0288 i2s_port2: port@2 {
0289 i2s_aux: endpoint {
0290 };
0291 };
0292
0293 spdif_port0: port@3 {
0294 spdif_hiecout1: endpoint {
0295 };
0296 };
0297
0298 spdif_port1: port@4 {
0299 spdif_iecout1: endpoint {
0300 };
0301 };
0302
0303 comp_spdif_port0: port@5 {
0304 comp_spdif_hiecout1: endpoint {
0305 };
0306 };
0307
0308 comp_spdif_port1: port@6 {
0309 comp_spdif_iecout1: endpoint {
0310 };
0311 };
0312 };
0313
0314 i2c0: i2c@58780000 {
0315 compatible = "socionext,uniphier-fi2c";
0316 status = "disabled";
0317 reg = <0x58780000 0x80>;
0318 #address-cells = <1>;
0319 #size-cells = <0>;
0320 interrupts = <0 41 4>;
0321 pinctrl-names = "default";
0322 pinctrl-0 = <&pinctrl_i2c0>;
0323 clocks = <&peri_clk 4>;
0324 resets = <&peri_rst 4>;
0325 clock-frequency = <100000>;
0326 };
0327
0328 i2c1: i2c@58781000 {
0329 compatible = "socionext,uniphier-fi2c";
0330 status = "disabled";
0331 reg = <0x58781000 0x80>;
0332 #address-cells = <1>;
0333 #size-cells = <0>;
0334 interrupts = <0 42 4>;
0335 pinctrl-names = "default";
0336 pinctrl-0 = <&pinctrl_i2c1>;
0337 clocks = <&peri_clk 5>;
0338 resets = <&peri_rst 5>;
0339 clock-frequency = <100000>;
0340 };
0341
0342 i2c2: i2c@58782000 {
0343 compatible = "socionext,uniphier-fi2c";
0344 status = "disabled";
0345 reg = <0x58782000 0x80>;
0346 #address-cells = <1>;
0347 #size-cells = <0>;
0348 interrupts = <0 43 4>;
0349 pinctrl-names = "default";
0350 pinctrl-0 = <&pinctrl_i2c2>;
0351 clocks = <&peri_clk 6>;
0352 resets = <&peri_rst 6>;
0353 clock-frequency = <100000>;
0354 };
0355
0356 i2c3: i2c@58783000 {
0357 compatible = "socionext,uniphier-fi2c";
0358 status = "disabled";
0359 reg = <0x58783000 0x80>;
0360 #address-cells = <1>;
0361 #size-cells = <0>;
0362 interrupts = <0 44 4>;
0363 pinctrl-names = "default";
0364 pinctrl-0 = <&pinctrl_i2c3>;
0365 clocks = <&peri_clk 7>;
0366 resets = <&peri_rst 7>;
0367 clock-frequency = <100000>;
0368 };
0369
0370 /* chip-internal connection for DMD */
0371 i2c4: i2c@58784000 {
0372 compatible = "socionext,uniphier-fi2c";
0373 reg = <0x58784000 0x80>;
0374 #address-cells = <1>;
0375 #size-cells = <0>;
0376 interrupts = <0 45 4>;
0377 clocks = <&peri_clk 8>;
0378 resets = <&peri_rst 8>;
0379 clock-frequency = <400000>;
0380 };
0381
0382 /* chip-internal connection for STM */
0383 i2c5: i2c@58785000 {
0384 compatible = "socionext,uniphier-fi2c";
0385 reg = <0x58785000 0x80>;
0386 #address-cells = <1>;
0387 #size-cells = <0>;
0388 interrupts = <0 25 4>;
0389 clocks = <&peri_clk 9>;
0390 resets = <&peri_rst 9>;
0391 clock-frequency = <400000>;
0392 };
0393
0394 /* chip-internal connection for HDMI */
0395 i2c6: i2c@58786000 {
0396 compatible = "socionext,uniphier-fi2c";
0397 reg = <0x58786000 0x80>;
0398 #address-cells = <1>;
0399 #size-cells = <0>;
0400 interrupts = <0 26 4>;
0401 clocks = <&peri_clk 10>;
0402 resets = <&peri_rst 10>;
0403 clock-frequency = <400000>;
0404 };
0405
0406 system_bus: system-bus@58c00000 {
0407 compatible = "socionext,uniphier-system-bus";
0408 status = "disabled";
0409 reg = <0x58c00000 0x400>;
0410 #address-cells = <2>;
0411 #size-cells = <1>;
0412 pinctrl-names = "default";
0413 pinctrl-0 = <&pinctrl_system_bus>;
0414 };
0415
0416 smpctrl@59801000 {
0417 compatible = "socionext,uniphier-smpctrl";
0418 reg = <0x59801000 0x400>;
0419 };
0420
0421 sdctrl@59810000 {
0422 compatible = "socionext,uniphier-pxs2-sdctrl",
0423 "simple-mfd", "syscon";
0424 reg = <0x59810000 0x400>;
0425
0426 sd_clk: clock {
0427 compatible = "socionext,uniphier-pxs2-sd-clock";
0428 #clock-cells = <1>;
0429 };
0430
0431 sd_rst: reset {
0432 compatible = "socionext,uniphier-pxs2-sd-reset";
0433 #reset-cells = <1>;
0434 };
0435 };
0436
0437 perictrl@59820000 {
0438 compatible = "socionext,uniphier-pxs2-perictrl",
0439 "simple-mfd", "syscon";
0440 reg = <0x59820000 0x200>;
0441
0442 peri_clk: clock {
0443 compatible = "socionext,uniphier-pxs2-peri-clock";
0444 #clock-cells = <1>;
0445 };
0446
0447 peri_rst: reset {
0448 compatible = "socionext,uniphier-pxs2-peri-reset";
0449 #reset-cells = <1>;
0450 };
0451 };
0452
0453 emmc: mmc@5a000000 {
0454 compatible = "socionext,uniphier-sd-v3.1.1";
0455 status = "disabled";
0456 reg = <0x5a000000 0x800>;
0457 interrupts = <0 78 4>;
0458 pinctrl-names = "default";
0459 pinctrl-0 = <&pinctrl_emmc>;
0460 clocks = <&sd_clk 1>;
0461 reset-names = "host", "hw";
0462 resets = <&sd_rst 1>, <&sd_rst 6>;
0463 bus-width = <8>;
0464 cap-mmc-highspeed;
0465 cap-mmc-hw-reset;
0466 non-removable;
0467 };
0468
0469 sd: mmc@5a400000 {
0470 compatible = "socionext,uniphier-sd-v3.1.1";
0471 status = "disabled";
0472 reg = <0x5a400000 0x800>;
0473 interrupts = <0 76 4>;
0474 pinctrl-names = "default", "uhs";
0475 pinctrl-0 = <&pinctrl_sd>;
0476 pinctrl-1 = <&pinctrl_sd_uhs>;
0477 clocks = <&sd_clk 0>;
0478 reset-names = "host";
0479 resets = <&sd_rst 0>;
0480 bus-width = <4>;
0481 cap-sd-highspeed;
0482 sd-uhs-sdr12;
0483 sd-uhs-sdr25;
0484 sd-uhs-sdr50;
0485 };
0486
0487 soc_glue: soc-glue@5f800000 {
0488 compatible = "socionext,uniphier-pxs2-soc-glue",
0489 "simple-mfd", "syscon";
0490 reg = <0x5f800000 0x2000>;
0491
0492 pinctrl: pinctrl {
0493 compatible = "socionext,uniphier-pxs2-pinctrl";
0494 };
0495 };
0496
0497 soc-glue@5f900000 {
0498 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
0499 "simple-mfd";
0500 #address-cells = <1>;
0501 #size-cells = <1>;
0502 ranges = <0 0x5f900000 0x2000>;
0503
0504 efuse@100 {
0505 compatible = "socionext,uniphier-efuse";
0506 reg = <0x100 0x28>;
0507 };
0508
0509 efuse@200 {
0510 compatible = "socionext,uniphier-efuse";
0511 reg = <0x200 0x58>;
0512 };
0513 };
0514
0515 xdmac: dma-controller@5fc10000 {
0516 compatible = "socionext,uniphier-xdmac";
0517 reg = <0x5fc10000 0x5300>;
0518 interrupts = <0 188 4>;
0519 dma-channels = <16>;
0520 #dma-cells = <2>;
0521 };
0522
0523 aidet: interrupt-controller@5fc20000 {
0524 compatible = "socionext,uniphier-pxs2-aidet";
0525 reg = <0x5fc20000 0x200>;
0526 interrupt-controller;
0527 #interrupt-cells = <2>;
0528 };
0529
0530 timer@60000200 {
0531 compatible = "arm,cortex-a9-global-timer";
0532 reg = <0x60000200 0x20>;
0533 interrupts = <1 11 0xf04>;
0534 clocks = <&arm_timer_clk>;
0535 };
0536
0537 timer@60000600 {
0538 compatible = "arm,cortex-a9-twd-timer";
0539 reg = <0x60000600 0x20>;
0540 interrupts = <1 13 0xf04>;
0541 clocks = <&arm_timer_clk>;
0542 };
0543
0544 intc: interrupt-controller@60001000 {
0545 compatible = "arm,cortex-a9-gic";
0546 reg = <0x60001000 0x1000>,
0547 <0x60000100 0x100>;
0548 #interrupt-cells = <3>;
0549 interrupt-controller;
0550 };
0551
0552 sysctrl@61840000 {
0553 compatible = "socionext,uniphier-pxs2-sysctrl",
0554 "simple-mfd", "syscon";
0555 reg = <0x61840000 0x10000>;
0556
0557 sys_clk: clock {
0558 compatible = "socionext,uniphier-pxs2-clock";
0559 #clock-cells = <1>;
0560 };
0561
0562 sys_rst: reset {
0563 compatible = "socionext,uniphier-pxs2-reset";
0564 #reset-cells = <1>;
0565 };
0566
0567 pvtctl: pvtctl {
0568 compatible = "socionext,uniphier-pxs2-thermal";
0569 interrupts = <0 3 4>;
0570 #thermal-sensor-cells = <0>;
0571 socionext,tmod-calibration = <0x0f86 0x6844>;
0572 };
0573 };
0574
0575 eth: ethernet@65000000 {
0576 compatible = "socionext,uniphier-pxs2-ave4";
0577 status = "disabled";
0578 reg = <0x65000000 0x8500>;
0579 interrupts = <0 66 4>;
0580 pinctrl-names = "default";
0581 pinctrl-0 = <&pinctrl_ether_rgmii>;
0582 clock-names = "ether";
0583 clocks = <&sys_clk 6>;
0584 reset-names = "ether";
0585 resets = <&sys_rst 6>;
0586 phy-mode = "rgmii-id";
0587 local-mac-address = [00 00 00 00 00 00];
0588 socionext,syscon-phy-mode = <&soc_glue 0>;
0589
0590 mdio: mdio {
0591 #address-cells = <1>;
0592 #size-cells = <0>;
0593 };
0594 };
0595
0596 usb0: usb@65a00000 {
0597 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0598 status = "disabled";
0599 reg = <0x65a00000 0xcd00>;
0600 interrupt-names = "dwc_usb3";
0601 interrupts = <0 134 4>;
0602 pinctrl-names = "default";
0603 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
0604 clock-names = "ref", "bus_early", "suspend";
0605 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
0606 resets = <&usb0_rst 15>;
0607 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
0608 <&usb0_ssphy0>, <&usb0_ssphy1>;
0609 dr_mode = "host";
0610 };
0611
0612 usb-glue@65b00000 {
0613 compatible = "socionext,uniphier-pxs2-dwc3-glue",
0614 "simple-mfd";
0615 #address-cells = <1>;
0616 #size-cells = <1>;
0617 ranges = <0 0x65b00000 0x400>;
0618
0619 usb0_rst: reset@0 {
0620 compatible = "socionext,uniphier-pxs2-usb3-reset";
0621 reg = <0x0 0x4>;
0622 #reset-cells = <1>;
0623 clock-names = "link";
0624 clocks = <&sys_clk 14>;
0625 reset-names = "link";
0626 resets = <&sys_rst 14>;
0627 };
0628
0629 usb0_vbus0: regulator@100 {
0630 compatible = "socionext,uniphier-pxs2-usb3-regulator";
0631 reg = <0x100 0x10>;
0632 clock-names = "link";
0633 clocks = <&sys_clk 14>;
0634 reset-names = "link";
0635 resets = <&sys_rst 14>;
0636 };
0637
0638 usb0_vbus1: regulator@110 {
0639 compatible = "socionext,uniphier-pxs2-usb3-regulator";
0640 reg = <0x110 0x10>;
0641 clock-names = "link";
0642 clocks = <&sys_clk 14>;
0643 reset-names = "link";
0644 resets = <&sys_rst 14>;
0645 };
0646
0647 usb0_hsphy0: hs-phy@200 {
0648 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
0649 reg = <0x200 0x10>;
0650 #phy-cells = <0>;
0651 clock-names = "link", "phy";
0652 clocks = <&sys_clk 14>, <&sys_clk 16>;
0653 reset-names = "link", "phy";
0654 resets = <&sys_rst 14>, <&sys_rst 16>;
0655 vbus-supply = <&usb0_vbus0>;
0656 };
0657
0658 usb0_hsphy1: hs-phy@210 {
0659 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
0660 reg = <0x210 0x10>;
0661 #phy-cells = <0>;
0662 clock-names = "link", "phy";
0663 clocks = <&sys_clk 14>, <&sys_clk 16>;
0664 reset-names = "link", "phy";
0665 resets = <&sys_rst 14>, <&sys_rst 16>;
0666 vbus-supply = <&usb0_vbus1>;
0667 };
0668
0669 usb0_ssphy0: ss-phy@300 {
0670 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
0671 reg = <0x300 0x10>;
0672 #phy-cells = <0>;
0673 clock-names = "link", "phy";
0674 clocks = <&sys_clk 14>, <&sys_clk 17>;
0675 reset-names = "link", "phy";
0676 resets = <&sys_rst 14>, <&sys_rst 17>;
0677 vbus-supply = <&usb0_vbus0>;
0678 };
0679
0680 usb0_ssphy1: ss-phy@310 {
0681 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
0682 reg = <0x310 0x10>;
0683 #phy-cells = <0>;
0684 clock-names = "link", "phy";
0685 clocks = <&sys_clk 14>, <&sys_clk 18>;
0686 reset-names = "link", "phy";
0687 resets = <&sys_rst 14>, <&sys_rst 18>;
0688 vbus-supply = <&usb0_vbus1>;
0689 };
0690 };
0691
0692 usb1: usb@65c00000 {
0693 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0694 status = "disabled";
0695 reg = <0x65c00000 0xcd00>;
0696 interrupt-names = "dwc_usb3";
0697 interrupts = <0 137 4>;
0698 pinctrl-names = "default";
0699 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
0700 clock-names = "ref", "bus_early", "suspend";
0701 clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
0702 resets = <&usb1_rst 15>;
0703 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
0704 dr_mode = "host";
0705 };
0706
0707 usb-glue@65d00000 {
0708 compatible = "socionext,uniphier-pxs2-dwc3-glue",
0709 "simple-mfd";
0710 #address-cells = <1>;
0711 #size-cells = <1>;
0712 ranges = <0 0x65d00000 0x400>;
0713
0714 usb1_rst: reset@0 {
0715 compatible = "socionext,uniphier-pxs2-usb3-reset";
0716 reg = <0x0 0x4>;
0717 #reset-cells = <1>;
0718 clock-names = "link";
0719 clocks = <&sys_clk 15>;
0720 reset-names = "link";
0721 resets = <&sys_rst 15>;
0722 };
0723
0724 usb1_vbus0: regulator@100 {
0725 compatible = "socionext,uniphier-pxs2-usb3-regulator";
0726 reg = <0x100 0x10>;
0727 clock-names = "link";
0728 clocks = <&sys_clk 15>;
0729 reset-names = "link";
0730 resets = <&sys_rst 15>;
0731 };
0732
0733 usb1_vbus1: regulator@110 {
0734 compatible = "socionext,uniphier-pxs2-usb3-regulator";
0735 reg = <0x110 0x10>;
0736 clock-names = "link";
0737 clocks = <&sys_clk 15>;
0738 reset-names = "link";
0739 resets = <&sys_rst 15>;
0740 };
0741
0742 usb1_hsphy0: hs-phy@200 {
0743 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
0744 reg = <0x200 0x10>;
0745 #phy-cells = <0>;
0746 clock-names = "link", "phy";
0747 clocks = <&sys_clk 15>, <&sys_clk 20>;
0748 reset-names = "link", "phy";
0749 resets = <&sys_rst 15>, <&sys_rst 20>;
0750 vbus-supply = <&usb1_vbus0>;
0751 };
0752
0753 usb1_hsphy1: hs-phy@210 {
0754 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
0755 reg = <0x210 0x10>;
0756 #phy-cells = <0>;
0757 clock-names = "link", "phy";
0758 clocks = <&sys_clk 15>, <&sys_clk 20>;
0759 reset-names = "link", "phy";
0760 resets = <&sys_rst 15>, <&sys_rst 20>;
0761 vbus-supply = <&usb1_vbus1>;
0762 };
0763
0764 usb1_ssphy0: ss-phy@300 {
0765 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
0766 reg = <0x300 0x10>;
0767 #phy-cells = <0>;
0768 clock-names = "link", "phy";
0769 clocks = <&sys_clk 15>, <&sys_clk 21>;
0770 reset-names = "link", "phy";
0771 resets = <&sys_rst 15>, <&sys_rst 21>;
0772 vbus-supply = <&usb1_vbus0>;
0773 };
0774 };
0775
0776 nand: nand-controller@68000000 {
0777 compatible = "socionext,uniphier-denali-nand-v5b";
0778 status = "disabled";
0779 reg-names = "nand_data", "denali_reg";
0780 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
0781 #address-cells = <1>;
0782 #size-cells = <0>;
0783 interrupts = <0 65 4>;
0784 pinctrl-names = "default";
0785 pinctrl-0 = <&pinctrl_nand>;
0786 clock-names = "nand", "nand_x", "ecc";
0787 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
0788 reset-names = "nand", "reg";
0789 resets = <&sys_rst 2>, <&sys_rst 2>;
0790 };
0791 };
0792 };
0793
0794 #include "uniphier-pinctrl.dtsi"
